Re: [PATCH 1/6] iommu/qcom: Use the asid read from device-tree if specified

On 31.05.2022 22:57, Rob Clark wrote: > On Tue, May 31, 2022 at 9:19 AM Will Deacon wrote: >> >> On Tue, May 31, 2022 at 09:15:22AM -0700, Rob Clark wrote: >>> On Tue, May 31, 2022 at 8:46 AM Will Deacon wrote: On Fri, May 27, 2022 at 11:28:56PM +0200, Konrad Dybcio wrote: >

Re: [PATCH 5/6] iommu/qcom: Index contexts by asid number to allow asid 0

On Fri, May 27, 2022 at 11:29:00PM +0200, Konrad Dybcio wrote: > From: AngeloGioacchino Del Regno > > This driver was indexing the contexts by asid-1, which is probably > done under the assumption that the first ASID is always 1. > > Unfortunately this is not entirely true: at least in the

Re: [PATCH v2 0/9] Add dynamic iommu backed bounce buffers

On Fri, 2022-05-27 at 10:25 +0900, David Stevens wrote: > On Tue, May 24, 2022 at 9:27 PM Niklas Schnelle > wrote: > > On Fri, 2021-08-06 at 19:34 +0900, David Stevens wrote: > > > From: David Stevens > > > > > > This patch series adds support for per-domain dynamic pools of iommu > > > bounce

[PATCH v1 7/7] iommu/amd: Introduce amd_iommu_pgtable command-line option

From: Suravee Suthikulpanit To allow specification whether to use v1 or v2 IOMMU pagetable for DMA remapping when calling kernel DMA-API. Co-developed-by: Vasant Hegde Signed-off-by: Vasant Hegde Signed-off-by: Suravee Suthikulpanit --- Documentation/admin-guide/kernel-parameters.txt | 6

[PATCH v1 6/7] iommu/amd: Add support for using AMD IOMMU v2 page table for DMA-API

From: Suravee Suthikulpanit Introduce init function for setting up DMA domain for DMA-API with the IOMMU v2 page table. Signed-off-by: Suravee Suthikulpanit Signed-off-by: Vasant Hegde --- drivers/iommu/amd/iommu.c | 21 + 1 file changed, 21 insertions(+) diff --git

[PATCH v1 5/7] iommu/amd: Add support for Guest IO protection

From: Suravee Suthikulpanit AMD IOMMU introduces support for Guest I/O protection where the request from the I/O device without a PASID are treated as if they have PASID 0. Co-developed-by: Vasant Hegde Signed-off-by: Vasant Hegde Signed-off-by: Suravee Suthikulpanit ---

[PATCH v1 4/7] iommu/amd: Initial support for AMD IOMMU v2 page table

Introduce IO page table framework support for AMD IOMMU v2 page table. This patch implements 4 level page table within iommu amd driver and supports 4K/2M/1G page sizes. Signed-off-by: Vasant Hegde --- drivers/iommu/amd/Makefile | 2 +- drivers/iommu/amd/amd_iommu_types.h | 5 +-

[PATCH v1 3/7] iommu/amd: Fix sparse warning

Fix below sparse warning: CHECK drivers/iommu/amd/iommu.c drivers/iommu/amd/iommu.c:73:24: warning: symbol 'amd_iommu_ops' was not declared. Should it be static? Also we are going to introduce v2 page table which has different pgsize_bitmaps. Hence remove 'const' qualifier. Signed-off-by:

[PATCH v1 2/7] iommu/amd: Update sanity check when enable PRI/ATS

From: Suravee Suthikulpanit Currently, PPR/ATS can be enabled only if the domain is type identity mapping. However, when we allow the IOMMU v2 page table to be used for DMA-API, the sanity check needs to be updated to only apply for the case when using AMD_IOMMU_V1 page table mode.

[PATCH v1 1/7] iommu/amd: Refactor amd_iommu_domain_enable_v2

From: Suravee Suthikulpanit The current function to enable IOMMU v2 also lock the domain. In order to reuse the same code in different code path, in which the domain has already been locked, refactor the function to separate the locking from the enabling logic. Co-developed-by: Vasant Hegde

[PATCH v1 0/7] iommu/amd: Add Generic IO Page Table Framework Support for v2 Page Table

This series introduces a new usage model for the v2 page table, where it can be used to implement support for DMA-API by adopting the generic IO page table framework. One of the target usecases is to support nested IO page tables where the guest uses the guest IO page table (v2) for translating