> From: Baolu Lu
> Sent: Tuesday, June 21, 2022 12:28 PM
>
> On 2022/6/21 11:46, Tian, Kevin wrote:
> >> From: Baolu Lu
> >> Sent: Tuesday, June 21, 2022 11:39 AM
> >>
> >> On 2022/6/21 10:54, Tian, Kevin wrote:
> From: Lu Baolu
> Sent: Monday, June 20, 2022 4:17 PM
> @@ -2564,7
On 2022/6/21 11:46, Tian, Kevin wrote:
From: Baolu Lu
Sent: Tuesday, June 21, 2022 11:39 AM
On 2022/6/21 10:54, Tian, Kevin wrote:
From: Lu Baolu
Sent: Monday, June 20, 2022 4:17 PM
@@ -2564,7 +2564,7 @@ static int domain_add_dev_info(struct
dmar_domain *domain, struct device *dev)
> From: Baolu Lu
> Sent: Tuesday, June 21, 2022 11:39 AM
>
> On 2022/6/21 10:54, Tian, Kevin wrote:
> >> From: Lu Baolu
> >> Sent: Monday, June 20, 2022 4:17 PM
> >> @@ -2564,7 +2564,7 @@ static int domain_add_dev_info(struct
> >> dmar_domain *domain, struct device *dev)
> >>
On 2022/6/21 10:54, Tian, Kevin wrote:
From: Lu Baolu
Sent: Monday, June 20, 2022 4:17 PM
@@ -2564,7 +2564,7 @@ static int domain_add_dev_info(struct
dmar_domain *domain, struct device *dev)
ret = intel_pasid_setup_second_level(iommu,
domain,
> From: Lu Baolu
> Sent: Monday, June 20, 2022 4:17 PM
> @@ -2564,7 +2564,7 @@ static int domain_add_dev_info(struct
> dmar_domain *domain, struct device *dev)
> ret = intel_pasid_setup_second_level(iommu,
> domain,
> dev,
Folks,
On Fri, Jun 10, 2022 at 11:08:02AM +0300, Serge Semin wrote:
> A basic device-specific linear memory mapping was introduced back in
> commit ("dma: Take into account dma_pfn_offset") as a single-valued offset
> preserved in the device.dma_pfn_offset field, which was initialized for
>
patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/intel-lab-lkp/linux/commits/Jean-Philippe-Brucker/uacce-Tidy-up-locking/20220620-220634
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git
Required for turning on per-process page tables for the GPU.
Signed-off-by: Emma Anholt
Reviewed-by: Konrad Dybcio
Reviewed-by: Dmitry Baryshkov
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
This is an SMMU for the adreno gpu, and adding this compatible lets
the driver use per-fd page tables, which are required for security
between GPU clients.
Signed-off-by: Emma Anholt
Reviewed-by: Dmitry Baryshkov
---
v2: moved qcom,adreno-smmu earlier
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2
This enable per-process page tables on the Qualcomm RB5 boards I'm
setting up for Mesa CI. Has survived a full deqp-vk run.
v2: moved qcom,adreno-smmu compatible earlier
Emma Anholt (2):
iommu: arm-smmu-impl: Add 8250 display compatible to the client list.
arm64: dts: qcom: sm8250: Enable
On Mon, Jun 20, 2022 at 02:24:31PM +0100, Jean-Philippe Brucker wrote:
> >From c7c2b051ec19285bbb973f8a2a5e58bb5326e00e Mon Sep 17 00:00:00 2001
> From: Jean-Philippe Brucker
> Date: Mon, 20 Jun 2022 10:10:41 +0100
> Subject: [PATCH] uacce: Tidy up locking
>
> The uacce driver must deal with a
On Mon, Jun 20, 2022 at 02:24:31PM +0100, Jean-Philippe Brucker wrote:
> On Fri, Jun 17, 2022 at 02:05:21PM +0800, Zhangfei Gao wrote:
> > > The refcount only ensures that the uacce_device object is not freed as
> > > long as there are open fds. But uacce_remove() can run while there are
> > >
On Fri, Jun 17, 2022 at 10:23:13PM +0800, Zhangfei Gao wrote:
> @@ -312,12 +345,20 @@ static ssize_t available_instances_show(struct device
> *dev,
> char *buf)
> {
> struct uacce_device *uacce = to_uacce_device(dev);
> + ssize_t ret;
>
> - if
On Fri, Jun 17, 2022 at 02:05:21PM +0800, Zhangfei Gao wrote:
> > The refcount only ensures that the uacce_device object is not freed as
> > long as there are open fds. But uacce_remove() can run while there are
> > open fds, or fds in the process of being opened. And atfer uacce_remove()
> >
On 2022-06-17 03:53, Tian, Kevin wrote:
From: Nicolin Chen
Sent: Friday, June 17, 2022 6:41 AM
...
- if (resv_msi) {
+ if (resv_msi && !domain->msi_cookie) {
ret = iommu_get_msi_cookie(domain->domain,
resv_msi_base);
if (ret && ret != -ENODEV)
On 2022/6/20 16:31, Yi Liu wrote:
Hi Baolu,
On 2022/6/20 16:17, Lu Baolu wrote:
The IOMMU driver shares the pasid table for PCI alias devices. When the
RID2PASID entry of the shared pasid table has been filled by the first
device, the subsequent devices will encounter the "DMAR: Setup
Hi Baolu,
On 2022/6/20 16:17, Lu Baolu wrote:
The IOMMU driver shares the pasid table for PCI alias devices. When the
RID2PASID entry of the shared pasid table has been filled by the first
device, the subsequent devices will encounter the "DMAR: Setup RID2PASID
failed" failure as the pasid
The IOMMU driver shares the pasid table for PCI alias devices. When the
RID2PASID entry of the shared pasid table has been filled by the first
device, the subsequent devices will encounter the "DMAR: Setup RID2PASID
failed" failure as the pasid entry has already been marke as present. As
the
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