[PATCH v2] memory: Add NVIDIA SMMU suspend/resume support

2014-12-23 Thread Mark Zhang
This patch adds suspend/resume support for NVIDIA SMMU. Signed-off-by: Mark Zhang ma...@nvidia.com --- Hi Alex/Olof/Thierry/Hiroshi, This patch is created on top of Thierry Reding's patch set: [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Changes since v1: - Remove the list

Re: [PATCH] memory: Add NVIDIA SMMU suspend/resume support

2014-12-22 Thread Mark Zhang
On 12/12/2014 04:18 PM, Alexandre Courbot wrote: Hi Mark, On Mon, Dec 8, 2014 at 3:20 PM, Mark Zhang ma...@nvidia.com wrote: This patch adds suspend/resume support for NVIDIA SMMU. This patch is created on top of Thierry Reding's patch set: [PATCH v7 00/12] NVIDIA Tegra memory

Re: [PATCH 4/6] iommu/tegra124: smmu: support more than 32 bit pa

2014-01-08 Thread Mark Zhang
On 01/08/2014 09:45 PM, Thierry Reding wrote: On Tue, Jan 07, 2014 at 01:25:37PM +0800, Mark Zhang wrote: On 12/05/2013 08:25 PM, Hiroshi Doyu wrote: [...] @@ -526,6 +530,21 @@ static int smmu_setup_regs(struct smmu_device *smmu) return 0; } +static void flush_ptc_by_addr(struct

Re: [PATCH 4/6] iommu/tegra124: smmu: support more than 32 bit pa

2014-01-06 Thread Mark Zhang
On 12/05/2013 08:25 PM, Hiroshi Doyu wrote: Add support for more than 32 bit physical address. If physical address space is 32bit, there will be no register write happening. Based on Pavan's internal patch. Signed-off-by: Hiroshi Doyu hd...@nvidia.com Cc: Pavan Kunapuli pkunap...@nvidia.com

Re: [PATCHv7 06/12] ARM: tegra: create a DT header defining SWGROUP ID

2013-12-18 Thread Mark Zhang
On 12/12/2013 03:57 PM, Hiroshi Doyu wrote: Create a header file to define the swgroup IDs used by the IOMMU(SMMU) binding. swgroup is a group of H/W clients which a Tegra SoC supports. This unique ID can be used to calculate MC_SMMU_swgroup name_ASID_0 register offset and MC_swgroup

Re: [v3 1/1] iommu/tegra: smmu: bus_notifier registers platform IOMMU devices

2012-12-19 Thread Mark Zhang
On 12/05/2012 02:37 AM, Hiroshi Doyu wrote: Most of platform devices are IOMMU'able in Tegra30 SoC. Registering all IOMMU'able devices manually isn't nice. This patch allows platform bus_notifier to register IOMMU devices. Map info can be passed from DT. Info format is: dma-window = 0

RE: Tegra DRM device tree bindings

2012-06-28 Thread Mark Zhang
Am Donnerstag, den 28.06.2012, 10:51 -0600 schrieb Stephen Warren: On 06/28/2012 05:12 AM, Thierry Reding wrote: On Wed, Jun 27, 2012 at 05:59:55PM +0200, Lucas Stach wrote: Am Mittwoch, den 27.06.2012, 16:44 +0200 schrieb Thierry Reding: ... In the ideal case I would want to not

RE: Tegra DRM device tree bindings

2012-06-27 Thread Mark Zhang
On Tue, 26 Jun 2012 12:55:13 +0200 Thierry Reding thierry.red...@avionic-design.de wrote: Old Signed by an unknown key Hi, while I haven't got much time to work on the actual code right now, I think it might still be useful if we could get the device tree binding to a

RE: Tegra DRM device tree bindings

2012-06-27 Thread Mark Zhang
On 06/26/2012 07:46 PM, Mark Zhang wrote: On Tue, 26 Jun 2012 12:55:13 +0200 Thierry Reding thierry.red...@avionic-design.de wrote: ... I'm not sure I understand how information about the carveout would be obtained from the IOMMU API, though. I think that can be similar with current