Hi Christoph,
On Mon, Aug 26, 2019 at 03:25:53PM +0200, Christoph Hellwig wrote:
> Based on an email from Paul Burton, quoting section 4.8 "Cacheability and
> Coherency Attributes and Access Types" of "MIPS Architecture Volume 1:
> Introduction to the MIPS32 Architecture&
an explicit arch opt-in.
>
> Signed-off-by: Christoph Hellwig
> Acked-by: Geert Uytterhoeven
For the MIPS bits:
Acked-by: Paul Burton
Thanks,
Paul
> ---
> arch/arm/Kconfig | 2 +-
> arch/arm/mm/dma-mapping.c | 6 --
> arch/a
Hi Christoph,
On Fri, Aug 16, 2019 at 09:07:48AM +0200, Christoph Hellwig wrote:
> I'd still like to hear a confirmation from the mips folks how
> the write combibe attribute can or can't work with the KSEG1
> uncached segment.
Quoting section 4.8 "Cacheability and Coherency Attributes and
for those configuration
> to fix a build failure as the arch_dma_prep_coherent symbol is also only
> provided for non-coherent platforms.
>
> Fixes: 2e96e04d25 ("MIPS: use the generic uncached segment support in
> dma-direct")
> Reported-by: Guenter Roeck
> Signed-off-by: C
Hi Christoph,
On Wed, May 01, 2019 at 07:49:05PM +0200, Christoph Hellwig wrote:
> On Wed, May 01, 2019 at 05:40:34PM +0000, Paul Burton wrote:
> > > > If it is necessary then as-is this code will clear the allocated memory
> > > > using uncached writes which will be pr
Hi Christoph,
On Wed, May 01, 2019 at 07:29:12PM +0200, Christoph Hellwig wrote:
> On Wed, May 01, 2019 at 05:18:59PM +0000, Paul Burton wrote:
> > I'm not so sure about this part though.
> >
> > On MIPS we currently don't clear the allocated memory with memset. Is
Hi Christoph,
On Tue, Apr 30, 2019 at 07:00:29AM -0400, Christoph Hellwig wrote:
> diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
> index 2c2772e9702a..d15a535c3e67 100644
> --- a/kernel/dma/direct.c
> +++ b/kernel/dma/direct.c
> @@ -164,6 +164,13 @@ void *dma_direct_alloc_pages(struct
ude/asm/page.h | 3 ---
> arch/mips/jazz/jazzdma.c | 6 --
> arch/mips/mm/dma-noncoherent.c | 26 +-
> 4 files changed, 10 insertions(+), 26 deletions(-)
This one looks good to me now, for patches 1 & 5:
Acked-
Hi Christoph,
On Tue, Apr 30, 2019 at 10:29:47PM +0200, Christoph Hellwig wrote:
> On Tue, Apr 30, 2019 at 08:10:43PM +0000, Paul Burton wrote:
> > This series looks like a nice cleanup to me - the one thing that puzzles
> > me is the !PageHighMem check above.
> >
&g
Hi Christoph,
On Tue, Apr 30, 2019 at 07:00:30AM -0400, Christoph Hellwig wrote:
> diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
> index f9549d2fbea3..f739f42c9d3c 100644
> --- a/arch/mips/mm/dma-noncoherent.c
> +++ b/arch/mips/mm/dma-noncoherent.c
> @@ -44,33
Hello,
Christoph Hellwig wrote:
> The DMA API generally relies on a struct device to work properly, and
> only barely works without one for legacy reasons. Pass the easily
> available struct device from the platform_device to remedy this.
>
> Also use GFP_KERNEL instead of GFP_ATOMIC as the
he actual
> users. Also rename the Kconfig option to describe the feature better.
>
> Signed-off-by: Christoph Hellwig
Acked-by: Paul Burton # MIPS
Thanks,
Paul
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10 --
> arch/mips/mm/dma-noncoherent.c | 8
Acked-by: Paul Burton # MIPS
Thanks,
Paul
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uld you like this to go through the MIPS tree or elsewhere? If the
latter:
Acked-by: Paul Burton
Thanks,
Paul
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Hi Maciej,
On Thu, Nov 01, 2018 at 07:54:24AM +, Maciej W. Rozycki wrote:
> Fix a MIPS `dma_alloc_coherent' regression from commit bc3ec75de545
> ("dma-mapping: merge direct and noncoherent ops") that causes a cached
> allocation to be returned on noncoherent cache systems.
>
> This is due
> config DMA_DIRECT_OPS
> > bool
> > depends on HAS_DMA
The change looks reasonable to me, so feel free to take your choice of:
Reviewed-by: Paul Burton
Acked-by: Paul Burton
My thought would be that it would be ideal to
ependencies:
>
> git://git.infradead.org/users/hch/misc.git dma-direct-noncoherent-merge
>
> Gitweb:
>
>
> http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/dma-direct-noncoherent-merge
Apart from the nits in patch 2, these look sane to me from a MIPS
p
Hi Christoph,
On Mon, Aug 27, 2018 at 04:50:29PM +0200, Christoph Hellwig wrote:
> Various architectures support both coherent and non-coherent dma on
> a per-device basis. Move the dma_noncoherent flag from mips the
> mips archdata field to struct device proper to prepare the
> infrastructure
Hi Christoph,
On Fri, Jul 27, 2018 at 07:26:06PM +0200, Christoph Hellwig wrote:
> mips_swiotlb_ops differs from the generic swiotlb_dma_ops only in that
> it contains a mb() barrier after each operations that maps or syncs
> dma memory to the device.
>
> The dma operations are defined to not be
Hi Christoph,
On Tue, Jul 10, 2018 at 02:35:18PM +0200, Christoph Hellwig wrote:
> On Wed, Jun 20, 2018 at 09:23:28AM +0200, Christoph Hellwig wrote:
> > No, this is a mixup. I hadn't noticed one case was 0x0fff and
> > the other 0x7fff.
> >
> > Below is the minimal fixup that keeps
Hi Christoph,
On Fri, Jun 15, 2018 at 01:08:47PM +0200, Christoph Hellwig wrote:
> -static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
> - dma_addr_t dma_addr)
> -{
> -#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
> - return (dma_addr > 0x8fff) ?
Hi Christoph,
On Fri, May 25, 2018 at 11:20:52AM +0200, Christoph Hellwig wrote:
> swiotlb_dma_supported will always return true for the a mask
> large enough to be covered by wired up physical address, so this
> function is pointless.
Shouldn't this be "large enough to cover all wired up
Hi Christoph,
For patches 1-4:
Reviewed-by: Paul Burton
Comment below for this patch though.
On Fri, May 25, 2018 at 11:20:51AM +0200, Christoph Hellwig wrote:
> diff --git a/arch/mips/cavium-octeon/dma-octeon.c
> b/arch/mips/cavium-octeon/dma-octeon.c
> index e5d00c79bd26..1e6
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