-secure world such as from kernel and requires SMC
calls to read them in the secure world. So, add this debug support
to dump implementation defined registers for TLB sync timeout issues.
Signed-off-by: Sai Prakash Ranjan
---
Changes in v3:
* Move this debug feature to arm-smmu-qcom-debug.c
Hi Robin,
On 7/6/2022 10:15 PM, Robin Murphy wrote:
On 2022-05-26 05:14, Sai Prakash Ranjan wrote:
TLB sync timeouts can be due to various reasons such as TBU power down
or pending TCU/TBU invalidation/sync and so on. Debugging these often
require dumping of some implementation defined
On 7/6/2022 5:26 PM, Will Deacon wrote:
On Thu, May 26, 2022 at 09:44:03AM +0530, Sai Prakash Ranjan wrote:
TLB sync timeouts can be due to various reasons such as TBU power down
or pending TCU/TBU invalidation/sync and so on. Debugging these often
require dumping of some implementation defined
On 6/23/2022 11:32 AM, Sai Prakash Ranjan wrote:
On 5/26/2022 9:44 AM, Sai Prakash Ranjan wrote:
TLB sync timeouts can be due to various reasons such as TBU power down
or pending TCU/TBU invalidation/sync and so on. Debugging these often
require dumping of some implementation defined registers
On 5/26/2022 9:44 AM, Sai Prakash Ranjan wrote:
TLB sync timeouts can be due to various reasons such as TBU power down
or pending TCU/TBU invalidation/sync and so on. Debugging these often
require dumping of some implementation defined registers to know the
status of TBU/TCU operations and some
Hi Vincent,
On 6/9/2022 2:52 AM, Vincent Knecht wrote:
Le jeudi 26 mai 2022 à 09:44 +0530, Sai Prakash Ranjan a écrit :
TLB sync timeouts can be due to various reasons such as TBU power down
or pending TCU/TBU invalidation/sync and so on. Debugging these often
require dumping of some
-secure world such as from kernel and requires SMC
calls to read them in the secure world. So, add this debug support
to dump implementation defined registers for TLB sync timeout issues.
Signed-off-by: Sai Prakash Ranjan
---
Changes in v2:
* Use scm call consistently so that it works on older
On 5/23/2022 10:48 PM, Sai Prakash Ranjan wrote:
TLB sync timeouts can be due to various reasons such as TBU power down
or pending TCU/TBU invalidation/sync and so on. Debugging these often
require dumping of some implementation defined registers to know the
status of TBU/TCU operations and some
-secure world such as from kernel and requires SMC
calls to read them in the secure world. So, add this debug support
to dump implementation defined registers for TLB sync timeout issues.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 50
On 2021-08-11 21:23, Robin Murphy wrote:
On 2021-08-11 11:30, Will Deacon wrote:
On Wed, Aug 11, 2021 at 11:37:25AM +0530, Sai Prakash Ranjan wrote:
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index f7da8953afbe..3904b598e0f9 100644
--- a/drivers
below:
There were reports of camera frame drops because of high overhead in
iommu unmap without this optimization because of frequent unmaps issued
by camera of about 100MB/s taking more than 100ms thereby causing frame
drops.
Signed-off-by: Sai Prakash Ranjan
---
Changes in v5:
* Drop non-strict mode
On 2021-08-11 16:00, Will Deacon wrote:
On Wed, Aug 11, 2021 at 11:37:25AM +0530, Sai Prakash Ranjan wrote:
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index f7da8953afbe..3904b598e0f9 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b
On 2021-08-10 23:38, Will Deacon wrote:
On Tue, Aug 03, 2021 at 11:09:17AM +0530, Sai Prakash Ranjan wrote:
On 2021-08-02 21:13, Will Deacon wrote:
> On Wed, Jun 23, 2021 at 07:12:01PM +0530, Sai Prakash Ranjan wrote:
> > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> >
issued
by camera of about 100MB/s taking more than 100ms thereby causing frame
drops.
Signed-off-by: Sai Prakash Ranjan
---
Changes in v4:
* Use a flag in struct arm_smmu_cfg to prefer TLBIASID (Will)
Changes in v3:
* Move the logic to arm-smmu driver from io-pgtable (Robin)
* Use a n
On 2021-08-10 14:46, Will Deacon wrote:
On Mon, Aug 09, 2021 at 11:17:40PM +0530, Sai Prakash Ranjan wrote:
On 2021-08-09 23:10, Will Deacon wrote:
> On Mon, Aug 09, 2021 at 10:18:21AM -0700, Rob Clark wrote:
> > On Mon, Aug 9, 2021 at 10:05 AM Will Deacon wrote:
> > > On
On 2021-08-03 11:36, Sai Prakash Ranjan wrote:
On 2021-08-02 21:42, Will Deacon wrote:
On Tue, Jul 27, 2021 at 03:03:22PM +0530, Sai Prakash Ranjan wrote:
Some clocks for SMMU can have parent as XO such as
gpu_cc_hub_cx_int_clk
of GPU SMMU in QTI SC7280 SoC and in order to enter deep sleep
and remove.
Signed-off-by: Sai Prakash Ranjan
Co-developed-by: Rajendra Nayak
Signed-off-by: Rajendra Nayak
---
Changes in v2:
* Add clk unprepare when clk enable fails in resume (Will)
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 26 +++---
1 file changed, 23 insertions
On 2021-08-10 00:00, Rob Clark wrote:
On Mon, Aug 9, 2021 at 11:11 AM Sai Prakash Ranjan
wrote:
On 2021-08-09 23:37, Rob Clark wrote:
> On Mon, Aug 9, 2021 at 10:47 AM Sai Prakash Ranjan
> wrote:
>>
>> On 2021-08-09 23:10, Will Deacon wrote:
>> > On Mon, Aug 09, 20
On 2021-08-09 23:37, Rob Clark wrote:
On Mon, Aug 9, 2021 at 10:47 AM Sai Prakash Ranjan
wrote:
On 2021-08-09 23:10, Will Deacon wrote:
> On Mon, Aug 09, 2021 at 10:18:21AM -0700, Rob Clark wrote:
>> On Mon, Aug 9, 2021 at 10:05 AM Will Deacon wrote:
>> >
>> > On
gt; > > > > > > On Thu, Jul 29, 2021 at 10:08:22AM +0530, Sai Prakash Ranjan
wrote:
> > > > > > > > On 2021-07-28 19:30, Georgi Djakov wrote:
> > > > > > > > > On Mon, Jan 11, 2021 at 07:45:02PM +0530, Sai Prakash Ran
On 2021-08-02 21:42, Will Deacon wrote:
On Tue, Jul 27, 2021 at 03:03:22PM +0530, Sai Prakash Ranjan wrote:
Some clocks for SMMU can have parent as XO such as
gpu_cc_hub_cx_int_clk
of GPU SMMU in QTI SC7280 SoC and in order to enter deep sleep states
in
such cases, we would need to drop the XO
On 2021-08-02 21:13, Will Deacon wrote:
On Wed, Jun 23, 2021 at 07:12:01PM +0530, Sai Prakash Ranjan wrote:
Currently for iommu_unmap() of large scatter-gather list with page
size
elements, the majority of time is spent in flushing of partial walks
in
__arm_lpae_unmap() which is a VA based
Hi Georgi,
On 2021-07-28 19:30, Georgi Djakov wrote:
On Mon, Jan 11, 2021 at 07:45:02PM +0530, Sai Prakash Ranjan wrote:
commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag")
removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went
the memory type settin
Hi Robin,
On 2021-07-27 16:03, Robin Murphy wrote:
On 2021-07-27 11:25, Robin Murphy wrote:
On 2021-07-27 10:33, Sai Prakash Ranjan wrote:
Some clocks for SMMU can have parent as XO such as
gpu_cc_hub_cx_int_clk
of GPU SMMU in QTI SC7280 SoC and in order to enter deep sleep states
,unprepare) in arm-smmu probe and remove.
Signed-off-by: Sai Prakash Ranjan
Co-developed-by: Rajendra Nayak
Signed-off-by: Rajendra Nayak
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm
Hi Robin, Will,
On 2021-07-12 09:39, Sai Prakash Ranjan wrote:
Hi Robin,
On 2021-06-23 19:12, Sai Prakash Ranjan wrote:
Currently for iommu_unmap() of large scatter-gather list with page
size
elements, the majority of time is spent in flushing of partial walks
in
__arm_lpae_unmap() which
Hi Robin,
On 2021-06-23 19:12, Sai Prakash Ranjan wrote:
Currently for iommu_unmap() of large scatter-gather list with page size
elements, the majority of time is spent in flushing of partial walks in
__arm_lpae_unmap() which is a VA based TLB invalidation invalidating
page-by-page on iommus
Hi Will,
On 2021-03-25 23:03, Will Deacon wrote:
On Tue, Mar 09, 2021 at 12:10:44PM +0530, Sai Prakash Ranjan wrote:
On 2021-02-05 17:38, Sai Prakash Ranjan wrote:
> On 2021-02-04 03:16, Will Deacon wrote:
> > On Tue, Feb 02, 2021 at 11:56:27AM +0530, Sai Prakash Ranjan wrote:
> &g
Hi Robin,
On 2021-06-23 00:07, Robin Murphy wrote:
On 2021-06-22 15:27, Sai Prakash Ranjan wrote:
Hi Robin,
On 2021-06-22 17:41, Robin Murphy wrote:
On 2021-06-22 08:11, Sai Prakash Ranjan wrote:
Hi Robin,
On 2021-06-21 21:15, Robin Murphy wrote:
On 2021-06-18 03:51, Sai Prakash Ranjan
e were reports of camera frame drops because of high overhead in
iommu unmap without this optimization because of frequent unmaps issued
by camera of about 100MB/s taking more than 100ms thereby causing frame
drops.
Signed-off-by: Sai Prakash Ranjan
---
Changes in v3:
* Move the logic to ar
Hi Robin,
On 2021-06-22 17:41, Robin Murphy wrote:
On 2021-06-22 08:11, Sai Prakash Ranjan wrote:
Hi Robin,
On 2021-06-21 21:15, Robin Murphy wrote:
On 2021-06-18 03:51, Sai Prakash Ranjan wrote:
Add a quirk IO_PGTABLE_QUIRK_TLB_INV_ALL to invalidate entire
context
with tlb_flush_all
Hi Robin,
On 2021-06-21 21:15, Robin Murphy wrote:
On 2021-06-18 03:51, Sai Prakash Ranjan wrote:
Add a quirk IO_PGTABLE_QUIRK_TLB_INV_ALL to invalidate entire context
with tlb_flush_all() callback in partial walk flush to improve unmap
performance on select few platforms where the cost
Hi,
On 2021-06-19 03:39, Doug Anderson wrote:
Hi,
On Thu, Jun 17, 2021 at 7:51 PM Sai Prakash Ranjan
wrote:
Currently for iommu_unmap() of large scatter-gather list with page
size
elements, the majority of time is spent in flushing of partial walks
in
__arm_lpae_unmap() which is a VA
On 2021-06-15 17:21, Sai Prakash Ranjan wrote:
> Hi Krishna,
>
> On 2021-06-14 23:18, Krishna Reddy wrote:
>>> Right but we won't know until we profile the specific usecases or try them
>>> in
>>> generic workload to see if they affect the perfo
erence in unmap performance as below:
There were reports of camera frame drops because of high overhead in
iommu unmap without this optimization because of frequent unmaps issued
by camera of about 100MB/s taking more than 100ms thereby causing frame
drops.
Signed-off-by: Sai Prakash
Set the pgtable quirk IO_PGTABLE_QUIRK_TLB_INV_ALL for QTI SoC
implementation to use ::tlb_flush_all() for partial walk flush
to improve unmap performance.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 11 +++
1 file changed, 11 insertions(+)
diff
Add a quirk IO_PGTABLE_QUIRK_TLB_INV_ALL to invalidate entire context
with tlb_flush_all() callback in partial walk flush to improve unmap
performance on select few platforms where the cost of over-invalidation
is less than the unmap latency.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu
choose tlb_flush_all in partial walk flush
* Set the quirk for QTI SoC implementation
Sai Prakash Ranjan (3):
iommu/io-pgtable: Add a quirk to use tlb_flush_all() for partial walk
flush
iommu/io-pgtable: Optimize partial walk flush for large scatter-gather
list
iommu/arm-smmu-qco
Hi Krishna,
On 2021-06-18 02:48, Krishna Reddy wrote:
Instead of flush_ops in init_context hook, perhaps a io_pgtable quirk
since this is
related to tlb, probably a bad name but IO_PGTABLE_QUIRK_TLB_INV which
will
be set in init_context impl hook and the prev condition in
On 2021-06-16 12:28, Sai Prakash Ranjan wrote:
Hi Robin,
On 2021-06-15 19:23, Robin Murphy wrote:
On 2021-06-15 12:51, Sai Prakash Ranjan wrote:
...
Hi @Robin, from these discussions it seems they are not ok with the
change
for all SoC vendor implementations and do not have any data
Hi Robin,
On 2021-06-15 19:23, Robin Murphy wrote:
On 2021-06-15 12:51, Sai Prakash Ranjan wrote:
...
Hi @Robin, from these discussions it seems they are not ok with the
change
for all SoC vendor implementations and do not have any data on such
impact.
As I mentioned above, on QCOM
Hi Krishna,
On 2021-06-14 23:18, Krishna Reddy wrote:
Right but we won't know until we profile the specific usecases or try
them in
generic workload to see if they affect the performance. Sure, over
invalidation is
a concern where multiple buffers can be mapped to same context and the
cache
Hi Krishna,
On 2021-06-11 22:19, Krishna Reddy wrote:
Hi Sai,
>> > No, the unmap latency is not just in some test case written, the
>> > issue is very real and we have workloads where camera is reporting
>> > frame drops because of this unmap latency in the order of 100s of
milliseconds.
Not
Hi Krishna,
On 2021-06-11 06:07, Krishna Reddy wrote:
> No, the unmap latency is not just in some test case written, the issue
> is very real and we have workloads where camera is reporting frame
> drops because of this unmap latency in the order of 100s of milliseconds.
> And hardware team
Hi Robin,
On 2021-06-10 20:59, Robin Murphy wrote:
On 2021-06-10 12:54, Sai Prakash Ranjan wrote:
Hi Robin,
On 2021-06-10 17:03, Robin Murphy wrote:
On 2021-06-10 10:36, Sai Prakash Ranjan wrote:
Hi Robin,
On 2021-06-10 14:38, Robin Murphy wrote:
On 2021-06-10 06:24, Sai Prakash Ranjan
Hi Robin,
On 2021-06-10 17:03, Robin Murphy wrote:
On 2021-06-10 10:36, Sai Prakash Ranjan wrote:
Hi Robin,
On 2021-06-10 14:38, Robin Murphy wrote:
On 2021-06-10 06:24, Sai Prakash Ranjan wrote:
Hi Robin,
On 2021-06-10 00:14, Robin Murphy wrote:
On 2021-06-09 15:53, Sai Prakash Ranjan
Hi Robin,
On 2021-06-10 14:38, Robin Murphy wrote:
On 2021-06-10 06:24, Sai Prakash Ranjan wrote:
Hi Robin,
On 2021-06-10 00:14, Robin Murphy wrote:
On 2021-06-09 15:53, Sai Prakash Ranjan wrote:
Currently for iommu_unmap() of large scatter-gather list with page
size
elements, the majority
Hi Robin,
On 2021-06-10 00:14, Robin Murphy wrote:
On 2021-06-09 15:53, Sai Prakash Ranjan wrote:
Currently for iommu_unmap() of large scatter-gather list with page
size
elements, the majority of time is spent in flushing of partial walks
in
__arm_lpae_unmap() which is a VA based TLB
16M 2391.890 us27.437 us
24M 3570.895 us39.937 us
32M 4755.234 us51.797 us
This is further reduced once the map/unmap_pages() support gets in which
will result in just 1 tlb_flush_all() as opposed to 16 tlb_flush_all().
Signed-off-by: Sai Praka
On 2021-06-08 17:31, Will Deacon wrote:
On Tue, Apr 20, 2021 at 11:34:55AM +0530, Sai Prakash Ranjan wrote:
Patch 1 adds the sc7280 smmu compatible.
Patch 2 moves the adreno smmu check before apss smmu to enable
adreno smmu specific implementation.
Note that dt-binding for sc7280 is already
Add compatible for SC7280 SMMU to use the Qualcomm Technologies, Inc.
specific implementation.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Bjorn Andersson
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu
ver reached because the current sequence checks
for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that
specific impl and we never reach adreno smmu specific implementation.
Suggested-by: Akhil P Oommen
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Bjorn Andersson
Acked-by: Jordan Cro
and reviews
* Rebase on top of for-joerg/arm-smmu/updates
Changes in v2:
* Add a comment to make sure this order is not changed in future (Jordan)
Sai Prakash Ranjan (2):
iommu/arm-smmu-qcom: Add SC7280 SMMU compatible
iommu/arm-smmu-qcom: Move the adreno smmu specific impl
drivers/iommu
Hi Will,
On 2021-05-24 08:13, Sai Prakash Ranjan wrote:
Hi Will,
On 2021-04-20 11:34, Sai Prakash Ranjan wrote:
Patch 1 adds the sc7280 smmu compatible.
Patch 2 moves the adreno smmu check before apss smmu to enable
adreno smmu specific implementation.
Note that dt-binding for sc7280
Hi Will,
On 2021-04-20 11:34, Sai Prakash Ranjan wrote:
Patch 1 adds the sc7280 smmu compatible.
Patch 2 moves the adreno smmu check before apss smmu to enable
adreno smmu specific implementation.
Note that dt-binding for sc7280 is already merged.
Changes in v3:
* Collect acks and reviews
On 2021-04-19 20:08, Bjorn Andersson wrote:
On Fri 26 Feb 03:55 CST 2021, Sai Prakash Ranjan wrote:
Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU
both implement "arm,mmu-500" in some QTI SoCs and to run through
adreno smmu specific implementation such as enab
ver reached because the current sequence checks
for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that
specific impl and we never reach adreno smmu specific implementation.
Suggested-by: Akhil P Oommen
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Bjorn Andersson
Acked-by: Jordan Cro
Add compatible for SC7280 SMMU to use the Qualcomm Technologies, Inc.
specific implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm
:
* Add a comment to make sure this order is not changed in future (Jordan)
Sai Prakash Ranjan (2):
iommu/arm-smmu-qcom: Add SC7280 SMMU compatible
iommu/arm-smmu-qcom: Move the adreno smmu specific impl earlier
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 14 +++---
1 file changed
On 2021-04-05 14:12, Sai Prakash Ranjan wrote:
Hi Bjorn,
On 2021-03-25 20:35, Will Deacon wrote:
On Thu, Mar 25, 2021 at 01:10:12PM +0530, Sai Prakash Ranjan wrote:
...
I think there is consensus on this series. I can resend if required
but it
still applies cleanly, let me know if you
Hi Bjorn,
On 2021-03-25 20:35, Will Deacon wrote:
On Thu, Mar 25, 2021 at 01:10:12PM +0530, Sai Prakash Ranjan wrote:
...
I think there is consensus on this series. I can resend if required
but it
still applies cleanly, let me know if you have any comments?
Please resend
Hi Will,
On 2021-03-15 00:31, Sai Prakash Ranjan wrote:
On 2021-03-12 04:59, Bjorn Andersson wrote:
On Sat 27 Feb 07:53 CST 2021, Sai Prakash Ranjan wrote:
Hi Bjorn,
On 2021-02-27 00:44, Bjorn Andersson wrote:
> On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:
>
>
> The current
On 2021-03-12 04:59, Bjorn Andersson wrote:
On Sat 27 Feb 07:53 CST 2021, Sai Prakash Ranjan wrote:
Hi Bjorn,
On 2021-02-27 00:44, Bjorn Andersson wrote:
> On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:
>
>
> The current logic picks one of:
> 1) is the compa
Hi,
On 2021-02-05 17:38, Sai Prakash Ranjan wrote:
On 2021-02-04 03:16, Will Deacon wrote:
On Tue, Feb 02, 2021 at 11:56:27AM +0530, Sai Prakash Ranjan wrote:
On 2021-02-01 23:50, Jordan Crouse wrote:
> On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
> > On Mon, Feb 1, 202
Hi Bjorn,
On 2021-02-27 00:44, Bjorn Andersson wrote:
> On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:
>
>
> The current logic picks one of:
> 1) is the compatible mentioned in qcom_smmu_impl_of_match[]
> 2) is the compatible an adreno
> 3) no quirks needed
>
> The change flips the order of
ver reached because the current sequence checks
for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that
specific impl and we never reach adreno smmu specific implementation.
Suggested-by: Akhil P Oommen
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qco
Add compatible for SC7280 SMMU to use the Qualcomm Technologies, Inc.
specific implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm
Patch 1 adds the sc7280 smmu compatible.
Patch 2 moves the adreno smmu check before apss smmu to enable
adreno smmu specific implementation.
Changes in v2:
* Add a comment to make sure this order is not changed in future (Jordan)
Sai Prakash Ranjan (2):
iommu/arm-smmu-qcom: Add SC7280 SMMU
On 2021-02-25 23:36, Jordan Crouse wrote:
On Thu, Feb 25, 2021 at 03:54:10PM +0530, Sai Prakash Ranjan wrote:
Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU
both implement "arm,mmu-500" in some QTI SoCs and to run through
adreno smmu specific implementation such a
ver reached because the current sequence checks
for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that
specific impl and we never reach adreno smmu specific implementation.
Suggested-by: Akhil P Oommen
Signed-off-by: Sai Prakash Ranjan
---
Its either this or we add a new compatible
Add compatible for SC7280 SMMU to use the Qualcomm Technologies, Inc.
specific implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm
Patch 1 adds the sc7280 smmu compatible.
Patch 2 moves the adreno smmu check before apss smmu to enable
adreno smmu specific implementation.
Sai Prakash Ranjan (2):
iommu/arm-smmu-qcom: Add SC7280 SMMU compatible
iommu/arm-smmu-qcom: Move the adreno smmu specific impl earlier
drivers/iommu
size=4096 unmapped_size=4096
After:
map: IOMMU: dev=1d84000.ufshc iova=0x000fffa88000
paddr=0x0001063db000 size=4096
unmap: IOMMU: dev=1d84000.ufshc iova=0x000fffa88000 size=4096
unmapped_size=4096
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/iommu.c| 8
On 2021-01-15 22:47, Robin Murphy wrote:
On 2021-01-15 15:14, Russell King - ARM Linux admin wrote:
On Mon, Jan 11, 2021 at 08:01:48PM +, Robin Murphy wrote:
On 2021-01-07 02:45, chenxiang (M) wrote:
Hi Will,� Robin or other guys,
When debugging SMMU/SVA issue on huawei ARM64 board, we
On 2021-02-04 03:16, Will Deacon wrote:
On Tue, Feb 02, 2021 at 11:56:27AM +0530, Sai Prakash Ranjan wrote:
On 2021-02-01 23:50, Jordan Crouse wrote:
> On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
> > On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote:
> > > On
On 2021-02-01 23:50, Jordan Crouse wrote:
On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote:
>
> On Fri, Jan 29, 2021 at 03:12:59PM +0530, Sai Prakash Ranjan wrote:
> > On 2021-01-29 14:35, Will Deacon wrote:
> > >
On 2021-02-01 23:50, Jordan Crouse wrote:
On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote:
>
> On Fri, Jan 29, 2021 at 03:12:59PM +0530, Sai Prakash Ranjan wrote:
> > On 2021-01-29 14:35, Will Deacon wrote:
> > >
On 2021-01-29 14:35, Will Deacon wrote:
On Mon, Jan 11, 2021 at 07:45:04PM +0530, Sai Prakash Ranjan wrote:
Add a new page protection flag IOMMU_LLC which can be used
by non-coherent masters to set cacheable memory attributes
for an outer level of cache called as last-level cache or
system
On 2021-01-20 10:48, Sai Prakash Ranjan wrote:
On 2021-01-11 19:45, Sai Prakash Ranjan wrote:
commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag")
removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went
the memory type setting required for the non-cohere
On 2021-01-11 19:45, Sai Prakash Ranjan wrote:
commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag")
removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went
the memory type setting required for the non-coherent masters to use
system cache. Now that sy
address
space creation, in this case we set them for A6XX GPUs.
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++
drivers/gpu/drm/msm/msm_iommu.c | 3 +++
drivers/gpu/drm/msm/msm_mmu.h | 4
3 files changed, 10 insertions(+)
diff --git
such as video where this can be used for per-buffer based
mapping.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 3 +++
include/linux/iommu.h | 6 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
Rename last-level cache quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to
IO_PGTABLE_QUIRK_PTW_LLC which is used to set the required TCR
attributes for non-coherent page table walker to be more generic
and in sync with the upcoming page protection flag IOMMU_LLC.
Signed-off-by: Sai Prakash Ranjan
ction flag.
The series slightly depends on following 2 patches posted earlier and
is based on msm-next branch:
* https://lore.kernel.org/patchwork/patch/1363008/
* https://lore.kernel.org/patchwork/patch/1363010/
Sai Prakash Ranjan (3):
iommu/io-pgtable: Rename last-level c
On 2021-01-11 11:52, Sai Prakash Ranjan wrote:
Hi Isaac,
I gave this series a go on chromebook and saw these warnings
and several device probe failures, logs attached below:
WARN corresponds to this code in arm_lpae_map_by_pgsize()
if (WARN_ON(iaext || (paddr + size) >> cf
Hi Isaac,
On 2021-01-09 07:20, Isaac J. Manjarres wrote:
> The iommu_map_sg() code currently iterates through the given
> scatter-gather list, and in the worst case, invokes iommu_map()
> for each element in the scatter-gather list, which calls into
> the IOMMU driver through an indirect call.
On 2021-01-08 23:48, Will Deacon wrote:
On Fri, Jan 08, 2021 at 11:17:25AM +0530, Sai Prakash Ranjan wrote:
On 2021-01-07 22:27, isa...@codeaurora.org wrote:
> On 2021-01-06 03:56, Will Deacon wrote:
> > On Thu, Dec 24, 2020 at 12:10:07PM +0530, Sai Prakash Ranjan wrote:
>
On 2021-01-08 23:39, isa...@codeaurora.org wrote:
On 2021-01-07 21:47, Sai Prakash Ranjan wrote:
On 2021-01-07 22:27, isa...@codeaurora.org wrote:
On 2021-01-06 03:56, Will Deacon wrote:
On Thu, Dec 24, 2020 at 12:10:07PM +0530, Sai Prakash Ranjan wrote:
commit ecd7274fb4cd ("iommu: R
On 2021-01-07 22:27, isa...@codeaurora.org wrote:
On 2021-01-06 03:56, Will Deacon wrote:
On Thu, Dec 24, 2020 at 12:10:07PM +0530, Sai Prakash Ranjan wrote:
commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY
flag")
removed unused IOMMU_SYS_CACHE_ONLY prot flag
Hi Will,
On 2021-01-06 17:26, Will Deacon wrote:
On Thu, Dec 24, 2020 at 12:10:07PM +0530, Sai Prakash Ranjan wrote:
commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag")
removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went
the memory type settin
ed to mark the memory as normal sys-cached for GPU to use system cache.
Without this, the system cache lines are not allocated for GPU. We use
the IO_PGTABLE_QUIRK_ARM_OUTER_WBWA quirk instead of a page protection
flag as the flag cannot be exposed via DMA api because of no in-tree
users.
Signed-off-by: S
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 9 +
drivers/iommu/arm/arm-smmu/arm
Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
2 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index
Fix the checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
b
Changes in v2:
* Addressed review comments and rebased on top of Jordan's split
pagetables series
Jordan Crouse (1):
drm/msm/a6xx: Add support for using system cache on MMU500 based
targets
Sai Prakash Ranjan (6):
iommu/io-pgtable: Add a domain attribute for pagetable configuration
Prakash Ranjan
---
drivers/gpu/drm/msm/msm_drv.c | 8
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 5 +
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 49685571dc0e..a1e22b974b77
the right attributes to cache the
hardware pagetables into the system cache.
Signed-off-by: Sharat Masetty
[saiprakash.ranjan: fix to set attr before device attach to iommu and rebase]
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +
drivers
Add a quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to override
the outer-cacheability attributes set in the TCR for a
non-coherent page table walker when using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 10 --
include/linux/io-pgtable.h | 4
Now that we have a struct io_pgtable_domain_attr with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 15 +--
drivers/iommu/arm/arm
Add support for domain attribute DOMAIN_ATTR_IO_PGTABLE_CFG
to get/set pagetable configuration data which initially will
be used to set quirks and later can be extended to include
other pagetable configuration data.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c
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