[PATCH v3 4/8] genirq: Drop redundant irq_init_effective_affinity

It does exactly the same thing as irq_data_update_effective_affinity. Signed-off-by: Samuel Holland --- Changes in v3: - New patch to drop irq_init_effective_affinity kernel/irq/manage.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/kernel/irq/manage.c b

[PATCH v3 6/8] genirq: Add and use an irq_data_update_affinity helper

mask, following the pattern of irq_data_update_effective_affinity. This allows the getter function to return a const cpumask pointer. Signed-off-by: Samuel Holland --- Changes in v3: - New patch to introduce irq_data_update_affinity arch/alpha/kernel/irq.c | 2 +- arch/ia64/kernel

[PATCH v3 7/8] genirq: Return a const cpumask from irq_data_get_affinity_mask

the cpumask or immediately passed the modified mask to irq_set_affinity. Signed-off-by: Samuel Holland --- Changes in v3: - New patch to make the returned cpumasks const arch/mips/cavium-octeon/octeon-irq.c | 4 ++-- arch/sh/kernel/irq.c | 7 --- arch/x86/hyperv/irqdomain.c

[PATCH v3 5/8] genirq: Refactor accessors to use irq_data_get_affinity_mask

A couple of functions directly reference the affinity mask. Route them through irq_data_get_affinity_mask so they will pick up any refactoring done there. Signed-off-by: Samuel Holland --- (no changes since v1) include/linux/irq.h | 14 +++--- 1 file changed, 7 insertions(+), 7

[PATCH v3 1/8] irqchip/mips-gic: Only register IPI domain when SMP is enabled

robot Signed-off-by: Samuel Holland --- Changes in v3: - New patch to fix build errors in uniprocessor MIPS configs drivers/irqchip/Kconfig| 3 +- drivers/irqchip/irq-mips-gic.c | 80 +++--- 2 files changed, 56 insertions(+), 27 deletions(-) diff --git

[PATCH v3 2/8] genirq: GENERIC_IRQ_IPI depends on SMP

The generic IPI code depends on the IRQ affinity mask being allocated and initialized. This will not be the case if SMP is disabled. Fix up the remaining driver that selected GENERIC_IRQ_IPI in a non-SMP config. Reported-by: kernel test robot Signed-off-by: Samuel Holland --- (no changes since

[PATCH v3 3/8] genirq: GENERIC_IRQ_EFFECTIVE_AFF_MASK depends on SMP

An IRQ's effective affinity can only be different from its configured affinity if there are multiple CPUs. Make it clear that this option is only meaningful when SMP is enabled. Most of the relevant code in irqdesc.c is already hidden behind CONFIG_SMP anyway. Signed-off-by: Samuel Holland

[PATCH v3 0/8] genirq: Provide real IRQ affinity masks in non-SMP configs

to prevent GENERIC_IRQ_IPI from being selected on !SMP Samuel Holland (8): irqchip/mips-gic: Only register IPI domain when SMP is enabled genirq: GENERIC_IRQ_IPI depends on SMP genirq: GENERIC_IRQ_EFFECTIVE_AFF_MASK depends on SMP genirq: Drop redundant irq_init_effective_affinity genirq

[PATCH v3 8/8] genirq: Provide an IRQ affinity mask in non-SMP configs

allocating one per IRQ. By returning a real cpumask from irq_data_get_affinity_mask even when SMP is disabled, irqchip drivers which iterate over that mask will automatically do the right thing. Signed-off-by: Samuel Holland --- Changes in v3: - Use cpumask_of(0) instead of cpu_possible_mask

[PATCH 4/5] iommu/sun50i: Add support for the D1 variant

D1 contains an IOMMU similar to the one in the H6 SoC, but the D1 variant has no external reset signal. It also has some register definition changes, but none that affect the current driver. Signed-off-by: Samuel Holland --- drivers/iommu/sun50i-iommu.c | 4 1 file changed, 4 insertions

[PATCH 0/5] iommu/sun50i: Allwinner D1 support

-coherent, set it here */ dev->dma_coherent = coherent; + + if (iommu) + iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1); } Samuel Holland (5): dt-bindings: iommu: sun50i: Add compatible for Allwinner D1 iommu/sun50i: Support variants without an external re

[PATCH 3/5] iommu/sun50i: Ensure bypass is disabled

The H6 variant of the hardware disables bypass by default. The D1 variant of the hardware enables bypass for all masters by default. Since the driver expects bypass to be disabled, ensure that is the case. Signed-off-by: Samuel Holland --- drivers/iommu/sun50i-iommu.c | 2 ++ 1 file changed

[PATCH 1/5] dt-bindings: iommu: sun50i: Add compatible for Allwinner D1

D1 contains an IOMMU similar to the one in the H6 SoC, but the D1 variant has no external reset signal. Signed-off-by: Samuel Holland --- .../iommu/allwinner,sun50i-h6-iommu.yaml | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/Documentation

[PATCH 2/5] iommu/sun50i: Support variants without an external reset

The IOMMU in the Allwinner D1 SoC does not have an external reset line. Only attempt to get the reset on hardware variants which should have one according to the binding. And switch from the deprecated function to the explicit "exclusive" variant. Signed-off-by: Samuel Holland ---

[PATCH 5/5] iommu/sun50i: Ensure the IOMMU can be used for DMA

So far, the driver has relied on arch/arm64/Kconfig to select IOMMU_DMA. Unsurprisingly, this does not work on RISC-V, so the driver must select IOMMU_DMA itself. Signed-off-by: Samuel Holland --- drivers/iommu/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/Kconfig b