Preparing to migrate to use IO page table framework.
There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 18 ++
drivers/iommu/amd/io_pgtable.c | 473
drivers/iommu/amd/iommu.c | 476
To simplify the fetch_pte function. There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 2 +-
drivers/iommu/amd/io_pgtable.c | 13 +++--
drivers/iommu/amd/iommu.c | 4 +++-
3 files changed, 11 insertions(+), 8 deletions
And move declaration to header file so that they can be included across
multiple files. There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 3 +++
drivers/iommu/amd/iommu.c | 39 +--
2 files changed, 22
I found an issue w/ this series. Please ignore. I'll send out V3.
Regards,
Suravee
On 10/2/20 7:28 PM, Suravee Suthikulpanit wrote:
The framework allows callable implementation of IO page table.
This allows AMD IOMMU driver to switch between different types
of AMD IOMMU page tables (e.g. v1 vs
. (patch 2/13)
- Move amd_iommu_setup_io_pgtable_ops to iommu.c instead of io_pgtable.c
patch 13/13)
Suravee Suthikulpanit (13):
iommu/amd: Re-define amd_iommu_domain_encode_pgtable as inline
iommu/amd: Prepare for generic IO page table framework
iommu/amd: Move pt_root to to struct
Make use of the new struct amd_io_pgtable in preparation to remove
the struct domain_pgtable.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 1 +
drivers/iommu/amd/iommu.c | 25 ++---
2 files changed, 11 insertions(+), 15 deletions(-)
diff
To better organize the data structure since it contains IO page table
related information.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 2 +-
drivers/iommu/amd/amd_iommu_types.h | 2 +-
drivers/iommu/amd/iommu.c | 2 +-
3 files changed, 3 insertions
And move declaration to header file so that they can be included across
multiple files. There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 3 +++
drivers/iommu/amd/iommu.c | 39 +--
2 files changed, 22
Move the function to header file to allow inclusion in other files.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 13 +
drivers/iommu/amd/iommu.c | 10 --
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/amd
Add initial hook up code to implement generic IO page table framework.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/Kconfig | 1 +
drivers/iommu/amd/Makefile | 2 +-
drivers/iommu/amd/amd_iommu_types.h | 32 +
drivers/iommu/amd/io_pgtable.c
To simplify the fetch_pte function. There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 2 +-
drivers/iommu/amd/io_pgtable.c | 13 +++--
drivers/iommu/amd/iommu.c | 4 +++-
3 files changed, 11 insertions(+), 8 deletions
These implement map and unmap for AMD IOMMU v1 pagetable, which
will be used by the IO pagetable framework.
Also clean up unused extern function declarations.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 13 -
drivers/iommu/amd/io_pgtable.c | 25
Switch to using IO page table framework for AMD IOMMU v1 page table.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/iommu.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 77f44b927ae7
Preparing to migrate to use IO page table framework.
There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 18 ++
drivers/iommu/amd/io_pgtable.c | 473
drivers/iommu/amd/iommu.c | 476
There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/io_pgtable.c | 31 +++
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c
index a2acd7e85ec3
Since the IO page table root and mode parameters have been moved into
the struct amd_io_pg, the function is no longer needed. Therefore,
remove it along with the struct domain_pgtable.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 4 ++--
drivers/iommu/amd
This implements iova_to_phys for AMD IOMMU v1 pagetable,
which will be used by the IO page table framework.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/io_pgtable.c | 21 +
drivers/iommu/amd/iommu.c | 16 +---
2 files changed, 22 insertions
Introduce amd_iommu_free_pgtable helper function, which consolidates
logic for freeing page table.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 2 +-
drivers/iommu/amd/io_pgtable.c | 12 +++-
drivers/iommu/amd/iommu.c | 19 ++-
3 files
Joerg,
On 10/1/20 7:59 PM, Joerg Roedel wrote:
On Thu, Sep 24, 2020 at 05:50:37PM +0700, Suravee Suthikulpanit wrote:
On 9/24/20 5:34 PM, Joerg Roedel wrote:
Hi Suravee,
On Wed, Sep 23, 2020 at 10:14:29AM +, Suravee Suthikulpanit wrote:
The framework allows callable implementation
lso be affected if cmpxchg16b
is not supported (which is unprecedented for AMD processors w/ IOMMU).
Cc: sta...@vger.kernel.org
Fixes: 880ac60e2538 ("iommu/amd: Introduce interrupt remapping ops structure")
Reported-by: Sean Osborne
Signed-off-by: Suravee Suthikulpanit
Tested-by: Erik Rockst
Robin,
On 9/24/20 7:25 PM, Robin Murphy wrote:
+struct io_pgtable_ops *amd_iommu_setup_io_pgtable_ops(struct iommu_dev_data
*dev_data,
+ struct protection_domain *domain)
+{
+domain->iop.pgtbl_cfg = (struct io_pgtable_cfg) {
+.pgsize_bitmap=
On 9/24/20 5:34 PM, Joerg Roedel wrote:
Hi Suravee,
On Wed, Sep 23, 2020 at 10:14:29AM +, Suravee Suthikulpanit wrote:
The framework allows callable implementation of IO page table.
This allows AMD IOMMU driver to switch between different types
of AMD IOMMU page tables (e.g. v1 vs. v2
) to
Completion Wait Write-Back (CWWB) Range Limit register
and requires the IOMMU CWWB semaphore base and range to be programmed
in the register offset 0020h and 0028h accordingly.
Cc: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu_types.h | 1 +
drivers/iommu/amd
-and-more.pdf
Changes from V1: (https://lkml.org/lkml/2020/9/16/455)
- Patch 2/3: Fix up per Joerg's comments
Thank you,
Suravee
Suravee Suthikulpanit (3):
iommu: amd: Use 4K page for completion wait write-back semaphore
iommu: amd: Add support for RMP_PAGE_FAULT and RMP_HW_ERR
iommu: amd: Re
, which is incremented for every completion wait command.
Since this new scheme is also compatible with non-SNP mode,
generalize the driver to use 4K page for completion-wait semaphore in
both modes.
Cc: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu_types.h | 3
IOMMU SNP support introduces two new IOMMU events:
* RMP Page Fault event
* RMP Hardware Error event
Hence, add reporting functions for these events.
Cc: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu_types.h | 2 +
drivers/iommu/amd/iommu.c
On 9/18/20 4:31 PM, Joerg Roedel wrote:
Hi Suravee,
On Wed, Sep 16, 2020 at 01:55:48PM +, Suravee Suthikulpanit wrote:
+static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
+{
+ struct pci_dev *pdev;
+ struct iommu_dev_data *dev_data = NULL;
+ int devid
This implements iova_to_phys for AMD IOMMU v1 pagetable,
which will be used by the IO page table framework.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/io_pgtable.c | 21 +
drivers/iommu/amd/iommu.c | 16 +---
2 files changed, 22 insertions
To better organize the data structure since it contains IO page table
related information.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 2 +-
drivers/iommu/amd/amd_iommu_types.h | 2 +-
drivers/iommu/amd/iommu.c | 2 +-
3 files changed, 3 insertions
These implement map and unmap for AMD IOMMU v1 pagetable, which
will be used by the IO pagetable framework.
Also clean up unused extern function declarations.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 13 -
drivers/iommu/amd/io_pgtable.c | 25
Preparing to migrate to use IO page table framework.
There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 18 ++
drivers/iommu/amd/io_pgtable.c | 473
drivers/iommu/amd/iommu.c | 476
Since the IO page table root and mode parameters have been moved into
the struct amd_io_pg, the function is no longer needed. Therefore,
remove it along with the struct domain_pgtable.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 4 ++--
drivers/iommu/amd
Switch to using IO page table framework for AMD IOMMU v1 page table.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 3 +++
drivers/iommu/amd/iommu.c | 10 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd
Move the function to header file to allow inclusion in other files.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 13 +
drivers/iommu/amd/iommu.c | 10 --
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/amd
And move declaration to header file so that they can be included across
multiple files. There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 3 +++
drivers/iommu/amd/iommu.c | 39 +--
2 files changed, 22
Make use of the new struct amd_io_pgtable in preparation to remove
the struct domain_pgtable.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 1 +
drivers/iommu/amd/iommu.c | 25 ++---
2 files changed, 11 insertions(+), 15 deletions(-)
diff
To simplify the fetch_pte function. There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 2 +-
drivers/iommu/amd/io_pgtable.c | 13 +++--
drivers/iommu/amd/iommu.c | 4 +++-
3 files changed, 11 insertions(+), 8 deletions
Introduce amd_iommu_free_pgtable helper function, which consolidates
logic for freeing page table.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 2 +-
drivers/iommu/amd/io_pgtable.c | 12 +++-
drivers/iommu/amd/iommu.c | 19 ++-
3 files
There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/io_pgtable.c | 31 +++
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c
index 524c5406ccd6
be no functional change.
Subsequent series will introduce support for the AMD IOMMU v2 page table.
Thanks,
Suravee
Suravee Suthikulpanit (13):
iommu: amd: Re-define amd_iommu_domain_encode_pgtable as inline
iommu: amd: Prepare for generic IO page table framework
iommu: amd: Move pt_root to to struct
Add initial hook up code to implement generic IO page table framework.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/Kconfig | 1 +
drivers/iommu/amd/Makefile | 2 +-
drivers/iommu/amd/amd_iommu_types.h | 32 +++
drivers/iommu/amd/io_pgtable.c | 89
, which is incremented for every completion wait command.
Since this new scheme is also compatible with non-SNP mode,
generalize the driver to use 4K page for completion-wait semaphore in
both modes.
Cc: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu_types.h | 3
-and-more.pdf
Thank you,
Suravee
Suravee Suthikulpanit (3):
iommu: amd: Use 4K page for completion wait write-back semaphore
iommu: amd: Add support for RMP_PAGE_FAULT and RMP_HW_ERR
iommu: amd: Re-purpose Exclusion range registers to support SNP CWWB
drivers/iommu/amd/amd_iommu_types.h | 6
) to
Completion Wait Write-Back (CWWB) Range Limit register
and requires the IOMMU CWWB semaphore base and range to be programmed
in the register offset 0020h and 0028h accordingly.
Cc: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu_types.h | 1 +
drivers/iommu/amd
IOMMU SNP support introduces two new IOMMU events:
* RMP Page Fault event
* RMP Hardware Error event
Hence, add reporting functions for these events.
Cc: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu_types.h | 2 +
drivers/iommu/amd/iommu.c
C enabled.
Reported-by: Maxim Levitsky
Tested-by: Maxim Levitsky
Cc: Joao Martins
Fixes: e52d58d54a321 ("iommu/amd: Use cmpxchg_double() when updating 128-bit
IRTE")
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/iommu.c | 4
1 file changed, 4 insertions(+)
On 9/15/20 8:19 PM, Joao Martins wrote:
On 9/15/20 1:30 PM, Suravee Suthikulpanit wrote:
On 9/15/20 6:25 PM, Maxim Levitsky wrote:
On Mon, 2020-09-14 at 21:48 +0700, Suravee Suthikulpanit wrote:
Could you please try with the following patch instead?
--- a/drivers/iommu/amd/iommu.c
+++ b
On 9/15/20 6:25 PM, Maxim Levitsky wrote:
On Mon, 2020-09-14 at 21:48 +0700, Suravee Suthikulpanit wrote:
Maxim,
On 9/13/2020 7:42 PM, Maxim Levitsky wrote:
Commit e52d58d54a32 ("iommu/amd: Use cmpxchg_double() when updating 128-bit
IRTE")
accidentally removed an
Maxim,
On 9/13/2020 7:42 PM, Maxim Levitsky wrote:
Commit e52d58d54a32 ("iommu/amd: Use cmpxchg_double() when updating 128-bit
IRTE")
accidentally removed an assumption that modify_irte_ga always set the valid bit
and amd_iommu_activate_guest_mode relied on that.
Side effect of this is that
fore check 'entry' (see line 3867)
Fix this by moving the @valid assignment to after @entry has been checked
for NULL.
Cc: Suravee Suthikulpanit
Fixes: 26e495f34107 ("iommu/amd: Restore IRTE.RemapEn bit after programming
IRTE")
Reported-by: Dan Carpenter
Signed-off-by: Joao Martins
Currently, the RemapEn (valid) bit is accidentally cleared when
programming IRTE w/ guestMode=0. It should be restored to
the prior state.
Reviewed-by: Joao Martins
Signed-off-by: Suravee Suthikulpanit
Fixes: b9fc6b56f478 ("iommu/amd: Implements irq_set_vcpu_affinity() hook to
setup vapic
)
* Fix typo in comments and commit messages
* Fix logic to check for X86_FEATURE_CX16 support in patch 2/2
Thanks,
Suravee
Suravee Suthikulpanit (2):
iommu: amd: Restore IRTE.RemapEn bit after programming IRTE
iommu: amd: Use cmpxchg_double() when updating 128-bit IRTE
drivers/iommu/amd/Kconfig
lso be affected if cmpxchg16b
is not supported (which is unprecedented for AMD processors w/ IOMMU).
Reviewed-by: Joao Martins
Reported-by: Sean Osborne
Tested-by: Erik Rockstrom
Signed-off-by: Suravee Suthikulpanit
Fixes: 880ac60e2538 ("iommu/amd: Introduce interrupt remapping ops s
Hi,
I'll send out V2 with fixes to the review comments below ...
On 9/2/20 10:26 PM, Joao Martins wrote:
On 9/2/20 5:51 AM, Suravee Suthikulpanit wrote:
When using 128-bit interrupt-remapping table entry (IRTE) (a.k.a GA mode),
current driver disables interrupt remapping when it updates
.
Investigation has shown that the issue is in the code to update IRTE
while remapping is enabled. Please see patch 2/2 for detail discussion.
This serires has been tested running in the setup mentioned above
upto 96 hours w/o seeing issues.
Thanks,
Suravee
Suravee Suthikulpanit (2):
iommu: amd
Currently, the RemapEn (valid) bit is accidentally cleared when
programming IRTE w/ guestMode=0. It should be restored to
the prior state.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/iommu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/amd/iommu.c b/drivers
lso be affected if cmpxchg16b
is not supported (which is unprecedented for AMD processors w/ IOMMU).
Reported-by: Sean Osborne
Tested-by: Erik Rockstrom
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/Kconfig | 2 +-
drivers/iommu/amd/init.c | 21 +++--
drivers/iommu/
atch is not applicable in subsequent
kernel versions.
Cc: sta...@vger.kernel.org
Cc: iommu@lists.linux-foundation.org
Reported-by: Robert Lippert
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/amd_i
defaults back to KERN_DEFAULT loglevel.
*/
#define pr_cont(fmt, ...) \
printk(KERN_CONT fmt, ##__VA_ARGS__)
So, remove the line break, so only one line is logged.
Fixes: 3928aa3f57 ("iommu/amd: Detect and enable guest vAPIC support")
Cc: Suravee Suthikulpanit
Cc: iom
On 6/16/20 3:48 AM, Alexander Monakov wrote:
Alexander
On 6/1/20 4:01 PM, Alexander Monakov wrote:
On Mon, 1 Jun 2020, Suravee Suthikulpanit wrote:
Moving init_iommu_perf_ctr just after iommu_flush_all_caches resolves
the issue. This is the earliest point in amd_iommu_init_pci where
Reviewed-by: Suravee Suthikulpanit
Thanks,
Suravee
On 6/13/20 6:11 AM, Jerry Snitselaar wrote:
Move AMD Kconfig and Makefile bits down into the amd directory
with the rest of the AMD specific files.
Cc: Joerg Roedel
Cc: Suravee Suthikulpanit
Signed-off-by: Jerry Snitselaar
---
drivers
Alexander
On 6/1/20 4:01 PM, Alexander Monakov wrote:
On Mon, 1 Jun 2020, Suravee Suthikulpanit wrote:
Moving init_iommu_perf_ctr just after iommu_flush_all_caches resolves
the issue. This is the earliest point in amd_iommu_init_pci where the
call succeeds on my laptop.
According to your
Hi Alexander,
On 5/30/20 3:07 AM, Alexander Monakov wrote:
The driver performs an extra check if the IOMMU's capabilities advertise
presence of performance counters: it verifies that counters are writable
by writing a hard-coded value to a counter and testing that reading that
counter gives
ze_t instead of int to pass parameter to __unmap_single().
Reported-by: Robert Lippert
Signed-off-by: Suravee Suthikulpanit
---
Note: This patch is intended for stable tree prior 5.5 due to commit
be62dbf554c5 ("iommu/amd: Convert AMD iommu driver to the dma-iommu api"),
where the function
e mode 100644 drivers/iommu/amd_iommu.h
Thank you for cleaning up.
Reviewed-by: Suravee Suthikulpanit
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
Ping.
Thanks,
Suravee
On 4/22/20 8:30 PM, Suravee Suthikulpanit wrote:
Currently, system fails to boot because the legacy interrupt remapping
mode does not enable 128-bit IRTE (GA), which is required for x2APIC
support.
Fix by using AMD_IOMMU_GUEST_IR_LEGACY_GA mode when booting with
kernel
GASup and automatically fallback to using
AMD_IOMMU_GUEST_IR_LEGACY if GA mode is not supported.
Fixes: 3928aa3f5775 ("iommu/amd: Detect and enable guest vAPIC support")
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_init.c | 2 +-
1 file changed, 1 insertion(+),
ir_data when calling modify_irte_ga() as done previously.
Fixes: b9c6ff94e43a ("iommu/amd: Re-factor guest virtual APIC (de-)activation
code")
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iom
amd_iommu_0/cmd_processed/
0 amd_iommu_1/cmd_processed/
472 amd_iommu_2/cmd_processed/
2 amd_iommu_3/cmd_processed/
10.198257728 seconds time elapsed
Reviewed-by: Suravee Suthikulpanit
Tested-by: Suravee Suthikulpanit
Thanks,
.
Reviewed-by: Suravee Suthikulpanit
Thanks,
Suravee
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
section "IOMMU x2APIC Support" of
the AMD I/O Virtualization Technology (IOMMU) Specification.
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 21 -
drivers/iommu/amd_iommu_init.c | 25 +++--
dri
Currently, the driver only supports lower 32-bit of IOMMU Control register.
However, newer AMD IOMMU specification has extended this register
to 64-bit. Therefore, replace the accessing API with the 64-bit version.
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu
odify detect_extended_topology() to return result")
* 3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function 0xB
when available")
Thanks,
Suravee
Changes from V1 (https://lkml.org/lkml/2018/6/22/645):
* 3/3: Declare the variable amd_iommu_xt_mode as static (per kbuild test
robot)
Sura
-off-by: Suravee Suthikulpanit
---
arch/x86/include/asm/irq_remapping.h | 5 +
include/linux/dmar.h | 5 -
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/irq_remapping.h
b/arch/x86/include/asm/irq_remapping.h
index 023b4a9..5f26962
section "IOMMU x2APIC Support" of
the AMD I/O Virtualization Technology (IOMMU) Specification.
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 21 -
drivers/iommu/amd_iommu_init.c | 25 +++--
dri
Currently, the driver only supports lower 32-bit of IOMMU Control register.
However, newer AMD IOMMU specification has extended this register
to 64-bit. Therefore, replace the accessing API with the 64-bit version.
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu
-off-by: Suravee Suthikulpanit
---
arch/x86/include/asm/irq_remapping.h | 5 +
include/linux/dmar.h | 5 -
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/irq_remapping.h
b/arch/x86/include/asm/irq_remapping.h
index 023b4a9..5f26962
odify detect_extended_topology() to return result")
* 3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function 0xB
when available")
Thanks,
Suravee
Suravee Suthikulpanit (3):
x86: irq_remapping: Move irq remapping mode enum
iommu/amd: Add support for higher 64-bit IOMMU Control Regis
.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 14 +-
drivers/iommu/amd_iommu_init.c | 19 +--
drivers/iommu/amd_iommu_proto.h | 2 ++
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu
This interface allows removal of IOMMU from a bus if needed.
For example, when the IOMMU driver fails to initialize, it should
unassociate itself from the bus (i.e. removing IOMMU groups and
unregister bus notifier block).
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/iommu.c | 22
should also be taken care of (e.g. removing
IOMMU groups, and unsetting bus IOMMU).
NOTE: This issue was found when booting Linux with pci=nomsi option.
Since the AMD IOMMU requires MSI, this result in failure to
initialize IOMMU interrupt.
Thanks,
Suravee
Suravee Suthikulpanit (2
Ping..
Joerg, when you get a chance, would you please let me know if you have any
other concerns for this v4.
Thanks,
Suravee
On 2/21/18 2:19 PM, Suravee Suthikulpanit wrote:
Since AMD IOMMU driver currently flushes all TLB entries
when page size is more than one, use the same interface
Since AMD IOMMU driver currently flushes all TLB entries
when page size is more than one, use the same interface
for both iommu_ops.flush_iotlb_all() and iommu_ops.iotlb_sync().
Cc: Joerg Roedel <j...@8bytes.org>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
Hi Joerg,
On 2/13/18 8:29 PM, Joerg Roedel wrote:
Hi Suravee,
thanks for working on this.
On Wed, Jan 31, 2018 at 12:01:14AM -0500, Suravee Suthikulpanit wrote:
+static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
+ unsigned long iova
Cc: Alex Williamson <alex.william...@redhat.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
---
Note: This issue was previously discussed here
(https://lkml.org/lkml/2018/1/30/873).
drivers/iommu/amd_iommu.c | 2 +-
drivers/iommu/iommu.c | 6 +++---
include/l
Hi Robin,
On 2/1/18 1:02 AM, Robin Murphy wrote:
Hi Suravee,
On 31/01/18 01:48, Suravee Suthikulpanit wrote:
Currently, iommu_unmap and iommu_unmap_fast return unmapped
pages with size_t. However, the actual value returned could
be error codes (< 0), which can be misinterpreted as la
Implement the newly added IOTLB flushing interface for AMD IOMMU.
Cc: Joerg Roedel <j...@8bytes.org>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
---
Changes from v2 (https://lkml.org/lkml/2017/12/27/44)
* Call domain_flush_complete() after domain_f
Change iommu_unmap[_fast] interfaces return type to ssize_t since
it can also return error code.
Cc: Joerg Roedel <j...@8bytes.org>
Cc: Alex Williamson <alex.william...@redhat.com>
Suravee Suthikulpanit (2):
iommu: Fix iommu_unmap and iommu_unmap_fast return type
vfio/type1: Add
Cc: Alex Williamson <alex.william...@redhat.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
---
drivers/iommu/amd_iommu.c | 6 +++---
drivers/iommu/intel-iommu.c | 4 ++--
drivers/iommu/iommu.c | 16
include/linux/iommu.h | 20 ++
Besides zero check the number of unmapped page, also check
and handle iommu_unmap errors.
Cc: Alex Williamson <alex.william...@redhat.com>
Cc: Joerg Roedel <j...@8bytes.org>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
---
drivers/vfio/vfio_iommu_type1.c
Hi Joerg,
On 12/27/17 4:20 PM, Suravee Suthikulpanit wrote:
Implement the newly added IOTLB flushing interface for AMD IOMMU.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
---
drivers/iommu/amd_iommu.c | 73 -
d
Alex / Joerg,
On 1/24/18 5:04 AM, Alex Williamson wrote:
@@ -648,12 +685,40 @@ static int vfio_iommu_type1_unpin_pages(void *iommu_data,
return i > npage ? npage : (i > 0 ? i : -EINVAL);
}
+static size_t try_unmap_unpin_fast(struct vfio_domain *domain, dma_addr_t iova,
+
Alex/Joerg,
On 1/24/18 5:04 AM, Alex Williamson wrote:
+static size_t try_unmap_unpin_fast(struct vfio_domain *domain, dma_addr_t iova,
+ size_t len, phys_addr_t phys,
+ struct list_head *unmapped_regions)
+{
+ struct
on AMD IOMMU with certain dGPUs.
This can be avoided by using the new IOTLB flushing interface.
Cc: Alex Williamson <alex.william...@redhat.com>
Cc: Joerg Roedel <jroe...@suse.de>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
---
Changes from V2: (https://lkm
Hi Joerg,
Do you have any feedback regarding this patch for AMD IOMMU? I'm re-sending the
patch 1/2
separately per Alex's suggestion.
Thanks,
Suravee
On 12/27/17 4:20 PM, Suravee Suthikulpanit wrote:
Implement the newly added IOTLB flushing interface for AMD IOMMU.
Signed-off-by: Suravee
Hi Alex,
On 1/9/18 3:53 AM, Alex Williamson wrote:
On Wed, 27 Dec 2017 04:20:34 -0500
Suravee Suthikulpanit <suravee.suthikulpa...@amd.com> wrote:
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index e30e29a..f000844 100644
--- a/drivers/vfio/vfio_iommu_t
Hi Alex,
On 1/9/18 4:07 AM, Alex Williamson wrote:
@@ -661,6 +705,8 @@ static long vfio_unmap_unpin(struct vfio_iommu *iommu,
struct vfio_dma *dma,
if (!IS_IOMMU_CAP_DOMAIN_IN_CONTAINER(iommu))
return 0;
+ INIT_LIST_HEAD(_regions);
+
/*
* We use the
Implement the newly added IOTLB flushing interface for AMD IOMMU.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
---
drivers/iommu/amd_iommu.c | 73 -
drivers/iommu/amd_iommu_init.c | 7
drivers/iommu/amd_iommu_t
: Alex Williamson <alex.william...@redhat.com>
Cc: Joerg Roedel <jroe...@suse.de>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
---
drivers/vfio/vfio_iommu_type1.c | 89 +++--
1 file changed, 77 insertions(+), 12 deleti
From: Suravee Suthikulpanit <ssuth...@redhat.com>
Currently, when pass-through dGPU to a guest VM, there are thousands
of IOTLB flush commands sent from IOMMU to end-point-device. This cause
performance issue when launching new VMs, and could cause IOTLB invalidate
time-out issue on certain
101 - 200 of 346 matches
Mail list logo
