On 30.10.2014 12:03, Alexandre Courbot wrote:
I had to change the .reg of TEGRA_SWGROUP_GPU to 0xaac to get the IOMMU
to work with GK20A. The reason is still not completely clear to me, but
if you look at the TRM you see that 0xaa8 is basically constant, with
the SMMU translation bit hardcoded
On 30.10.2014 12:22, Alexandre Courbot wrote:
So should I understand that the GPU group is for addresses without bit
34 set (hence forcibly disabled) while GPUB is used when that bit is
set? Or is it something else?
That's exactly correct. And only GPUB can be programmed to be SMMU
translated.
On 30.10.2014 15:35, Alexandre Courbot wrote:
Great, thanks for confirming!
Thierry, how do you want to address this? We could change the register
for the GPU group, or (maybe preferable if we want to reflect the actual
hardware state) add the GPUB group. I don't know if that would be easy
On 21.05.2012 16:58, Thierry Reding wrote:
I agree that reflecting the hardware hierarchy within the device tree makes
sense. I'll need to add some code to tear down child devices in the cleanup
path, but that shouldn't be too difficult.
However, adding a whole bus_type implementation would
On 21.05.2012 14:05, Thierry Reding wrote:
I agree. It's really just a simple-bus kind of bus. Except that it'll need
another compatible value to make the host1x driver bind to it. But we should
be able to make it work without creating a completely new bus. I guess the
ranges property could
