Re: [PATCH v2] iommu/arm-smmu-v3: Increase CMDQ drain timeout value

2017-05-29 Thread Sunil Kovvuri
On Fri, May 5, 2017 at 4:47 PM, wrote: > From: Sunil Goutham > > Processing queue full of TLB invalidation commands might > take more time on some platforms than current timeout > of 100us. So increased drain timeout value. > > Also now udelay time

[PATCH v2] iommu/arm-smmu-v3: Increase CMDQ drain timeout value

2017-05-05 Thread sunil . kovvuri
From: Sunil Goutham Processing queue full of TLB invalidation commands might take more time on some platforms than current timeout of 100us. So increased drain timeout value. Also now udelay time is increased exponentially for each poll. Signed-off-by: Sunil Goutham

Re: [PATCH] iommu/arm-smmu-v3: Poll for CMDQ drain completion more effectively

2017-05-03 Thread Sunil Kovvuri
On Wed, May 3, 2017 at 9:29 PM, Will Deacon <will.dea...@arm.com> wrote: > On Wed, May 03, 2017 at 09:24:13PM +0530, Sunil Kovvuri wrote: >> On Wed, May 3, 2017 at 9:07 PM, Will Deacon <will.dea...@arm.com> wrote: >> > On Wed, May 03, 2017 at 06:49:09PM +0530, Sun

Re: [PATCH] iommu/arm-smmu-v3: Poll for CMDQ drain completion more effectively

2017-05-03 Thread Sunil Kovvuri
On Wed, May 3, 2017 at 9:07 PM, Will Deacon <will.dea...@arm.com> wrote: > On Wed, May 03, 2017 at 06:49:09PM +0530, Sunil Kovvuri wrote: >> On Thu, Apr 27, 2017 at 4:43 PM, <sunil.kovv...@gmail.com> wrote: >> > From: Sunil Goutham <sgout...@cavium.com> >>

Re: [PATCH] iommu/arm-smmu-v3: Poll for CMDQ drain completion more effectively

2017-05-03 Thread Sunil Kovvuri
On Thu, Apr 27, 2017 at 4:43 PM, wrote: > From: Sunil Goutham > > Modified polling on CMDQ consumer similar to how polling is done for TLB SYNC > completion in SMMUv2 driver. Code changes are done with reference to > > 8513c8930069 iommu/arm-smmu:

Re: [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-04-27 Thread Sunil Kovvuri
On Thu, Apr 27, 2017 at 7:09 PM, Robert Richter wrote: > On 27.04.17 17:16:21, Geetha sowjanya wrote: >> From: Geetha >> >> Cavium CN99xx SMMUv3 implementation has two Silicon Erratas. >> 1. Errata ID #74 >>SMMU register alias Page 1 is not

[PATCH] iommu/arm-smmu-v3: Poll for CMDQ drain completion more effectively

2017-04-27 Thread sunil . kovvuri
From: Sunil Goutham Modified polling on CMDQ consumer similar to how polling is done for TLB SYNC completion in SMMUv2 driver. Code changes are done with reference to 8513c8930069 iommu/arm-smmu: Poll for TLB sync completion more effectively Poll timeout has been increased

Re: [PATCH v2] iommu/arm-smmu: Return IOVA in iova_to_phys when SMMU is bypassed

2017-04-26 Thread Sunil Kovvuri
On Wed, Apr 26, 2017 at 5:06 PM, Will Deacon <will.dea...@arm.com> wrote: > On Wed, Apr 26, 2017 at 04:13:29PM +0530, Sunil Kovvuri wrote: >> On Wed, Apr 26, 2017 at 3:31 PM, Will Deacon <will.dea...@arm.com> wrote: >> > Hi Sunil, >> > >> > On T

Re: [PATCH v2] iommu/arm-smmu: Return IOVA in iova_to_phys when SMMU is bypassed

2017-04-26 Thread Sunil Kovvuri
On Wed, Apr 26, 2017 at 3:31 PM, Will Deacon wrote: > Hi Sunil, > > On Tue, Apr 25, 2017 at 03:27:52PM +0530, sunil.kovv...@gmail.com wrote: >> From: Sunil Goutham >> >> For software initiated address translation, when domain type is >>

Re: [PATCH] iommu/arm-smmu-v3: Increase SMMU CMD queue poll timeout

2017-04-26 Thread Sunil Kovvuri
On Mon, Apr 24, 2017 at 10:35 PM, Will Deacon <will.dea...@arm.com> wrote: > On Mon, Apr 24, 2017 at 10:26:53PM +0530, Sunil Kovvuri wrote: >> On Mon, Apr 24, 2017 at 9:38 PM, Will Deacon <will.dea...@arm.com> wrote: >> > On Mon, Apr 24, 2017 at 05:29:36PM +0530, Gee

Re: [PATCH v2] iommu/arm-smmu: Return IOVA in iova_to_phys when SMMU is bypassed

2017-04-26 Thread Sunil Kovvuri
On Tue, Apr 25, 2017 at 3:27 PM, wrote: > From: Sunil Goutham > > For software initiated address translation, when domain type is > IOMMU_DOMAIN_IDENTITY i.e SMMU is bypassed, mimic HW behavior > i.e return the same IOVA as translated address. > >

[PATCH v2] iommu/arm-smmu: Return IOVA in iova_to_phys when SMMU is bypassed

2017-04-25 Thread sunil . kovvuri
From: Sunil Goutham For software initiated address translation, when domain type is IOMMU_DOMAIN_IDENTITY i.e SMMU is bypassed, mimic HW behavior i.e return the same IOVA as translated address. This patch is an extension to Will Deacon's patchset "Implement SMMU passthrough

Re: [PATCH] iommu/arm-smmu-v3: Increase SMMU CMD queue poll timeout

2017-04-24 Thread Sunil Kovvuri
On Mon, Apr 24, 2017 at 9:38 PM, Will Deacon wrote: > On Mon, Apr 24, 2017 at 05:29:36PM +0530, Geetha sowjanya wrote: >> From: Geetha >> >> When large memory is being unmapped, huge no of tlb invalidation cmds are >> submitted followed by a SYNC command.

Re: [PATCH] iommu/arm-smmu: Return IOVA in iova_to_phys when SMMU is bypassed

2017-04-24 Thread Sunil Kovvuri
On Mon, Apr 24, 2017 at 9:30 PM, Will Deacon <will.dea...@arm.com> wrote: > On Mon, Apr 24, 2017 at 09:23:16PM +0530, Sunil Kovvuri wrote: >> On Mon, Apr 24, 2017 at 8:14 PM, Will Deacon <will.dea...@arm.com> wrote: >> > On Mon, Apr 17, 2017 at 05:27:26PM +0530,

Re: [PATCH] iommu/arm-smmu: Return IOVA in iova_to_phys when SMMU is bypassed

2017-04-24 Thread Sunil Kovvuri
On Mon, Apr 24, 2017 at 8:14 PM, Will Deacon wrote: > On Mon, Apr 17, 2017 at 05:27:26PM +0530, sunil.kovv...@gmail.com wrote: >> From: Sunil Goutham >> >> For software initiated address translation, when domain type is >> IOMMU_DOMAIN_IDENTITY i.e SMMU

Re: [PATCH] iommu/arm-smmu: Return IOVA in iova_to_phys when SMMU is bypassed

2017-04-19 Thread Sunil Kovvuri
On Mon, Apr 17, 2017 at 5:27 PM, wrote: > From: Sunil Goutham > > For software initiated address translation, when domain type is > IOMMU_DOMAIN_IDENTITY i.e SMMU is bypassed, mimic HW behavior > i.e return the same IOVA as translated address. > >

[PATCH] iommu/arm-smmu: Return IOVA in iova_to_phys when SMMU is bypassed

2017-04-17 Thread sunil . kovvuri
From: Sunil Goutham For software initiated address translation, when domain type is IOMMU_DOMAIN_IDENTITY i.e SMMU is bypassed, mimic HW behavior i.e return the same IOVA as translated address. This patch is an extension to Will Deacon's patchset "Implement SMMU

Re: [RFC PATCH 4/7] ACPICA: IORT: Add SMMuV3 model definitions.

2017-04-11 Thread Sunil Kovvuri
On Tue, Apr 11, 2017 at 9:29 PM, Robin Murphy wrote: > On 11/04/17 15:42, linucher...@gmail.com wrote: >> From: Linu Cherian >> >> Add SMMuV3 model definitions. >> >> Signed-off-by: Linu Cherian >> --- >>

Re: [RFC PATCH 2/7] iommu/arm-smmu-v3: Do resource size checks based on smmu option PAGE0_REGS_ONLY

2017-04-11 Thread Sunil Kovvuri
On Tue, Apr 11, 2017 at 9:13 PM, Robin Murphy wrote: > On 11/04/17 15:42, linucher...@gmail.com wrote: >> From: Linu Cherian >> >> With implementations supporting only page 0 of register space, >> resource size can be 64k as well and hence perform

Re: [RFC PATCH 3/7] iommu/arm-smmu-v3: Introduce smmu option USE_SHARED_IRQS for Silicon errata

2017-04-11 Thread Sunil Kovvuri
On Tue, Apr 11, 2017 at 9:51 PM, Will Deacon wrote: > On Tue, Apr 11, 2017 at 04:54:26PM +0100, Robin Murphy wrote: >> On 11/04/17 15:42, linucher...@gmail.com wrote: >> > From: Geetha >> > >> > Cavium 99xx SMMU implementation doesn't not support unique

Re: [PATCH] iommu/arm-smmu: Fix 16bit ASID configuration

2017-04-03 Thread Sunil Kovvuri
On Tue, Mar 28, 2017 at 4:11 PM, wrote: > From: Sunil Goutham > > 16bit ASID should be enabled before initializing TTBR0/1, > otherwise only LSB 8bit ASID will be considered. Hence > moving configuration of TTBCR register ahead of TTBR0/1 > while

Re: [RFC PATCH 04/30] iommu/arm-smmu-v3: Add support for PCI ATS

2017-04-03 Thread Sunil Kovvuri
On Mon, Apr 3, 2017 at 3:44 PM, Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> wrote: > On 03/04/17 09:34, Sunil Kovvuri wrote: >>> +static size_t arm_smmu_atc_invalidate_domain(struct arm_smmu_domain >>> *smmu_domain, >>> +

Re: [RFC PATCH 04/30] iommu/arm-smmu-v3: Add support for PCI ATS

2017-04-03 Thread Sunil Kovvuri
> +static size_t arm_smmu_atc_invalidate_domain(struct arm_smmu_domain > *smmu_domain, > +unsigned long iova, size_t size) > +{ > + unsigned long flags; > + struct arm_smmu_cmdq_ent cmd = {0}; > + struct arm_smmu_group *smmu_group; > +

[PATCH] iommu/arm-smmu: Fix 16bit ASID configuration

2017-03-28 Thread sunil . kovvuri
From: Sunil Goutham 16bit ASID should be enabled before initializing TTBR0/1, otherwise only LSB 8bit ASID will be considered. Hence moving configuration of TTBCR register ahead of TTBR0/1 while initializing context bank. Signed-off-by: Sunil Goutham

Re: [PATCH 5/4] iommu/arm-smmu: Poll for TLB sync completion more effectively

2017-03-27 Thread Sunil Kovvuri
On Thu, Mar 23, 2017 at 11:29 PM, Robin Murphy wrote: > On relatively slow development platforms and software models, the > inefficiency of our TLB sync loop tends not to show up - for instance on > a Juno r1 board I typically see the TLBI has completed of its own accord >