On Mon, Oct 28, 2019 at 12:37:28PM +0100, Christoph Hellwig wrote:
> On Mon, Oct 28, 2019 at 11:24:58AM +, Will Deacon wrote:
> > Agreed. The way I /think/ it works is that on many SoCs there is a
> > system/last-level cache (LLC) which effectively sits in front of memory for
> > all masters.
On Mon, Oct 28, 2019 at 11:59:04AM +, Robin Murphy wrote:
> On 28/10/2019 11:24, Will Deacon wrote:
> >Hi Christoph,
> >
> >On Mon, Oct 28, 2019 at 08:41:56AM +0100, Christoph Hellwig wrote:
> >>On Sat, Oct 26, 2019 at 03:12:57AM -0700, isa...@codeaurora.org wrote:
> >>>On 2019-10-25 22:30,
On 28/10/2019 11:24, Will Deacon wrote:
Hi Christoph,
On Mon, Oct 28, 2019 at 08:41:56AM +0100, Christoph Hellwig wrote:
On Sat, Oct 26, 2019 at 03:12:57AM -0700, isa...@codeaurora.org wrote:
On 2019-10-25 22:30, Christoph Hellwig wrote:
The definition makes very little sense.
Can you
On Mon, Oct 28, 2019 at 11:24:58AM +, Will Deacon wrote:
> Agreed. The way I /think/ it works is that on many SoCs there is a
> system/last-level cache (LLC) which effectively sits in front of memory for
> all masters. Even if a device isn't coherent with the CPU caches, we still
> want to be
Hi Christoph,
On Mon, Oct 28, 2019 at 08:41:56AM +0100, Christoph Hellwig wrote:
> On Sat, Oct 26, 2019 at 03:12:57AM -0700, isa...@codeaurora.org wrote:
> > On 2019-10-25 22:30, Christoph Hellwig wrote:
> >> The definition makes very little sense.
> > Can you please clarify what part doesn’t
On Sat, Oct 26, 2019 at 03:12:57AM -0700, isa...@codeaurora.org wrote:
> On 2019-10-25 22:30, Christoph Hellwig wrote:
>> The definition makes very little sense.
> Can you please clarify what part doesn’t make sense, and why?
It looks like complete garbage to me. That might just be because it
On 2019-10-25 22:30, Christoph Hellwig wrote:
The definition makes very little sense.
Can you please clarify what part doesn’t make sense, and why? This is
really just an extension of this patch that got mainlined, so that
clients that use the DMA API can use IOMMU_QCOM_SYS_CACHE as well:
The definition makes very little sense. Any without a user in the
same series it is a complete no-go anyway.
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Currently, IOMMU_QCOM_SYS_CACHE exists to allow non-coherent
I/O masters on Qualcomm SoCs to upgrade to caching their
buffers in the outer-level/system cache on these platforms.
However, these masters are limited to managing the mapping
of these buffers themselves through the IOMMU framework,
as
