Hi Jacob,
On 3/31/20 6:08 PM, Jacob Pan wrote:
> Actually, this is not a bug. The current code has:
> #define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
>
> Which already has the type and shift.
>
> In my vSVA series, I redefined granu such that I can use them in the 2D
> table
Actually, this is not a bug. The current code has:
#define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
Which already has the type and shift.
In my vSVA series, I redefined granu such that I can use them in the 2D
table lookup.
-#define QI_PC_ALL_PASIDS (QI_PC_TYPE |
Hi Jacob,
On 3/31/20 1:25 AM, Jacob Pan wrote:
> PASID cache type and shift of granularity bits are missing in
> the current code.
>
> Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table
> interface")
>
> Cc: Eric Auger
> Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Thanks
PASID cache type and shift of granularity bits are missing in
the current code.
Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table
interface")
Cc: Eric Auger
Signed-off-by: Jacob Pan
---
drivers/iommu/intel-pasid.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git