On Thu, May 26, 2022 at 10:29:09AM +0700, Suravee Suthikulpanit wrote:
> Actually, I am referring to when user uses the IOMMU v2 table for shared
> virtual address
> in current iommu_v2 driver (e.g. amd_iommu_init_device(),
> amd_iommu_bind_pasid).
>From what I can see this is not handled yet
Joerg,
On 5/20/22 3:09 PM, Joerg Roedel wrote:
Hi Suravee,
On Mon, May 16, 2022 at 07:27:51PM +0700, Suravee Suthikulpanit wrote:
- Also, it seems that the current iommu v2 page table use case, where
GVA->GPA=SPA
will no longer be supported on system w/ SNPSup=1. Any thoughts?
Support for
On 2022-05-20 09:58, Joerg Roedel wrote:
On Fri, May 20, 2022 at 09:54:51AM +0100, Robin Murphy wrote:
The .def_domain type op already allows drivers to do exactly this sort of
override. You could also conditionally reject IOMMU_DOMAIN_PASSTHROUGH in
.domain_alloc for good measure, provided
On Fri, May 20, 2022 at 09:54:51AM +0100, Robin Murphy wrote:
> The .def_domain type op already allows drivers to do exactly this sort of
> override. You could also conditionally reject IOMMU_DOMAIN_PASSTHROUGH in
> .domain_alloc for good measure, provided that (for now at least*) SNP is a
>
On 2022-05-20 09:09, Joerg Roedel wrote:
Hi Suravee,
On Mon, May 16, 2022 at 07:27:51PM +0700, Suravee Suthikulpanit wrote:
Due to the new restriction (please see the IOMMU spec Rev 3.06-PUB - Apr 2021
https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf) where the use of
DTE[Mode]=0 is
Hi Suravee,
On Mon, May 16, 2022 at 07:27:51PM +0700, Suravee Suthikulpanit wrote:
> Due to the new restriction (please see the IOMMU spec Rev 3.06-PUB - Apr 2021
> https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf) where the use of
> DTE[Mode]=0 is not supported on systems that are
Joerg,
On 5/13/22 8:07 PM, Joerg Roedel wrote:
On Mon, May 09, 2022 at 02:48:15AM -0500, Suravee Suthikulpanit wrote:
On AMD system with SNP enabled, IOMMU hardware checks the host translation
valid (TV) and guest translation valid (GV) bits in the device
table entry (DTE) before accessing the
On Mon, May 09, 2022 at 02:48:15AM -0500, Suravee Suthikulpanit wrote:
> On AMD system with SNP enabled, IOMMU hardware checks the host translation
> valid (TV) and guest translation valid (GV) bits in the device
> table entry (DTE) before accessing the corresponded page tables.
>
> However,
On AMD system with SNP enabled, IOMMU hardware checks the host translation
valid (TV) and guest translation valid (GV) bits in the device
table entry (DTE) before accessing the corresponded page tables.
However, current IOMMU driver sets the TV bit for all devices
regardless of whether the host
