On 2022/4/13 7:04, Tian, Kevin wrote:
From: Jason Gunthorpe
Sent: Tuesday, April 12, 2022 9:21 PM
On Tue, Apr 12, 2022 at 09:13:27PM +0800, Lu Baolu wrote:
btw as discussed in last version it is not necessarily to recalculate
snoop control globally with this new approach. Will follow up to
> From: Jason Gunthorpe
> Sent: Tuesday, April 12, 2022 9:21 PM
>
> On Tue, Apr 12, 2022 at 09:13:27PM +0800, Lu Baolu wrote:
>
> > > > > btw as discussed in last version it is not necessarily to recalculate
> > > > > snoop control globally with this new approach. Will follow up to
> > > > >
On Tue, Apr 12, 2022 at 09:13:27PM +0800, Lu Baolu wrote:
> > > > btw as discussed in last version it is not necessarily to recalculate
> > > > snoop control globally with this new approach. Will follow up to
> > > > clean it up after this series is merged.
> > > Agreed. But it also requires the
On 2022/4/12 15:44, Tian, Kevin wrote:
From: Lu Baolu
Sent: Saturday, April 9, 2022 8:51 PM
On 2022/4/8 16:16, Tian, Kevin wrote:
From: Jason Gunthorpe
Sent: Thursday, April 7, 2022 11:24 PM
IOMMU_CACHE means "normal DMA to this iommu_domain's IOVA
should
be cache
coherent" and is used by
> From: Lu Baolu
> Sent: Saturday, April 9, 2022 8:51 PM
>
> On 2022/4/8 16:16, Tian, Kevin wrote:
> >> From: Jason Gunthorpe
> >> Sent: Thursday, April 7, 2022 11:24 PM
> >>
> >> IOMMU_CACHE means "normal DMA to this iommu_domain's IOVA
> should
> >> be cache
> >> coherent" and is used by the
On Fri, Apr 08, 2022 at 09:47:57AM -0600, Alex Williamson wrote:
> > Ultimately VFIO plumbs the result of enforce_cache_coherency() back into
> > the x86 platform code through kvm_arch_register_noncoherent_dma() which
> > controls if the WBINVD instruction is available in the guest. No other
> >
On 2022/4/8 16:16, Tian, Kevin wrote:
From: Jason Gunthorpe
Sent: Thursday, April 7, 2022 11:24 PM
IOMMU_CACHE means "normal DMA to this iommu_domain's IOVA should
be cache
coherent" and is used by the DMA API. The definition allows for special
non-coherent DMA to exist - ie processing of the
On Thu, 7 Apr 2022 12:23:45 -0300
Jason Gunthorpe wrote:
> IOMMU_CACHE means "normal DMA to this iommu_domain's IOVA should be cache
> coherent" and is used by the DMA API. The definition allows for special
> non-coherent DMA to exist - ie processing of the no-snoop flag in PCIe
> TLPs - so
> From: Jason Gunthorpe
> Sent: Thursday, April 7, 2022 11:24 PM
>
> IOMMU_CACHE means "normal DMA to this iommu_domain's IOVA should
> be cache
> coherent" and is used by the DMA API. The definition allows for special
> non-coherent DMA to exist - ie processing of the no-snoop flag in PCIe
>
IOMMU_CACHE means "normal DMA to this iommu_domain's IOVA should be cache
coherent" and is used by the DMA API. The definition allows for special
non-coherent DMA to exist - ie processing of the no-snoop flag in PCIe
TLPs - so long as this behavior is opt-in by the device driver.
The flag is
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