Restrict the shareability domain when mapping buffers that are
GPU-visible only.
Signed-off-by: Boris Brezillon <boris.brezil...@collabora.com>
---
Flagged RFC because I'm not sure adding a new flag is the right
way to convey the 'dev-private buffer' information.
---
drivers/iommu/io-pgtable-arm.c | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index dd9e47189d0d..6ac3defb9ae1 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -450,16 +450,25 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct
arm_lpae_io_pgtable *data,
<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
}
- /*
- * Also Mali has its own notions of shareability wherein its Inner
- * domain covers the cores within the GPU, and its Outer domain is
- * "outside the GPU" (i.e. either the Inner or System domain in CPU
- * terms, depending on coherency).
- */
- if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
+ if (data->iop.fmt == ARM_MALI_LPAE) {
+ /*
+ * Mali has its own notions of shareability wherein its Inner
+ * domain covers the cores within the GPU, and its Outer domain
+ * is "outside the GPU" (i.e. either the Inner or System domain
+ * in CPU terms, depending on coherency).
+ * If the mapping is only device-visible, we can use the Inner
+ * domain, otherwise we need to stick to Outer domain
+ * shareability.
+ */
+ if (prot & IOMMU_DEVONLY)
+ pte |= ARM_LPAE_PTE_SH_IS;
+ else
+ pte |= ARM_LPAE_PTE_SH_OS;
+ } else if (prot & IOMMU_CACHE) {
pte |= ARM_LPAE_PTE_SH_IS;
- else
+ } else {
pte |= ARM_LPAE_PTE_SH_OS;
+ }
if (prot & IOMMU_NOEXEC)
pte |= ARM_LPAE_PTE_XN;
--
2.31.1
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