On 18/07/18 15:54, Joerg Roedel wrote:
> On Mon, Jul 16, 2018 at 03:28:14PM +0200, Matthias Brugger wrote:
.../devicetree/bindings/iommu/mediatek,iommu.txt | 6 +-
.../memory-controllers/mediatek,smi-common.txt | 6 +-
.../memory-controllers/mediatek,smi-larb.txt |
On Mon, Jul 16, 2018 at 03:28:14PM +0200, Matthias Brugger wrote:
> >> .../devicetree/bindings/iommu/mediatek,iommu.txt | 6 +-
> >> .../memory-controllers/mediatek,smi-common.txt | 6 +-
> >> .../memory-controllers/mediatek,smi-larb.txt | 5 +-
> >> include/dt-bindings/memory/mt271
On 21/06/18 08:27, Yong Wu wrote:
> Hi Matthias,
>
> A gentle ping on this.
>
> On Thu, 2018-05-24 at 20:35 +0800, Yong Wu wrote:
>> This patch adds decriptions for mt2712 IOMMU and SMI.
>>
>> In order to balance the bandwidth, mt2712 has two M4Us, two
>> smi-commons, 10 smi-larbs. and m
Hi Matthias,
A gentle ping on this.
On Thu, 2018-05-24 at 20:35 +0800, Yong Wu wrote:
> This patch adds decriptions for mt2712 IOMMU and SMI.
>
> In order to balance the bandwidth, mt2712 has two M4Us, two
> smi-commons, 10 smi-larbs. and mt2712 is also MTK IOMMU gen2 which
> uses ARM Shor
This patch adds decriptions for mt2712 IOMMU and SMI.
In order to balance the bandwidth, mt2712 has two M4Us, two
smi-commons, 10 smi-larbs. and mt2712 is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt2712 M4U-SMI HW diagram is as below:
