Re: [PATCH v4 4/7] iommu/vt-d: Setup pasid entries for iova over first level

2019-12-20 Thread Lu Baolu
Hi Yi, On 12/20/19 7:44 PM, Liu, Yi L wrote: From: Lu Baolu [mailto:baolu...@linux.intel.com] Sent: Thursday, December 19, 2019 11:17 AM To: Joerg Roedel ; David Woodhouse ; Alex Williamson Subject: [PATCH v4 4/7] iommu/vt-d: Setup pasid entries for iova over first level Intel VT-d

RE: [PATCH v4 4/7] iommu/vt-d: Setup pasid entries for iova over first level

2019-12-20 Thread Liu, Yi L
> From: Lu Baolu [mailto:baolu...@linux.intel.com] > Sent: Thursday, December 19, 2019 11:17 AM > To: Joerg Roedel ; David Woodhouse ; > Alex Williamson > Subject: [PATCH v4 4/7] iommu/vt-d: Setup pasid entries for iova over first > level > > Intel VT-d in scalable

[PATCH v4 4/7] iommu/vt-d: Setup pasid entries for iova over first level

2019-12-18 Thread Lu Baolu
Intel VT-d in scalable mode supports two types of page tables for IOVA translation: first level and second level. The IOMMU driver can choose one from both for IOVA translation according to the use case. This sets up the pasid entry if a domain is selected to use the first-level page table for