On Tue, Mar 28, 2017 at 7:43 PM, Rob Herring wrote:
> On Tue, Mar 28, 2017 at 12:27 AM, Oza Oza wrote:
>> On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring wrote:
>>> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep
>>>
On Wed, Mar 29, 2017 at 10:13 AM, Oza Oza wrote:
> On Tue, Mar 28, 2017 at 7:59 PM, Robin Murphy wrote:
>> On 28/03/17 06:27, Oza Oza wrote:
>>> On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring wrote:
On Sat, Mar 25, 2017 at 12:31
On Tue, Mar 28, 2017 at 7:59 PM, Robin Murphy wrote:
> On 28/03/17 06:27, Oza Oza wrote:
>> On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring wrote:
>>> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep
>>> wrote:
it is possible that
On 28/03/17 06:27, Oza Oza wrote:
> On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring wrote:
>> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep wrote:
>>> it is possible that PCI device supports 64-bit DMA addressing,
>>> and thus it's driver sets device's
On Tue, Mar 28, 2017 at 12:27 AM, Oza Oza wrote:
> On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring wrote:
>> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep wrote:
>>> it is possible that PCI device supports 64-bit DMA addressing,
>>>
On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring wrote:
> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep wrote:
>> it is possible that PCI device supports 64-bit DMA addressing,
>> and thus it's driver sets device's dma_mask to DMA_BIT_MASK(64),
>> however PCI
it is possible that PCI device supports 64-bit DMA addressing,
and thus it's driver sets device's dma_mask to DMA_BIT_MASK(64),
however PCI host bridge may have limitations on the inbound
transaction addressing. As an example, consider NVME SSD device
connected to iproc-PCIe controller.