On Mon, Feb 04, 2013 at 09:54:07PM +0100, Hiroshi Doyu wrote:
> Hiroshi Doyu wrote @ Mon, 04 Feb 2013 22:39:21 +0200 (EET):
>
> > > Upon reflection, that comment probably isn't correct, since the only way
> > > to know where each register range begins, relative to the register
> > > numbers that
Hiroshi Doyu wrote @ Mon, 04 Feb 2013 22:39:21 +0200 (EET):
> > Upon reflection, that comment probably isn't correct, since the only way
> > to know where each register range begins, relative to the register
> > numbers that the driver uses, is to calculate reg_base. So, I think you
> > do need r
Stephen Warren wrote @ Mon, 4 Feb 2013 21:35:45 +0100:
> >> This loop is purely for checking offset to be valid. And this loop is
> >> repeated in the smmu_write() function. I queued a patch on-top to make
> >> this more clear. Please double-check:
> >
> > Actually I did the similar thing in the
On 02/04/2013 01:31 PM, Hiroshi Doyu wrote:
> Hi Joerg,
>
> Joerg Roedel wrote @ Mon, 4 Feb 2013 20:53:32 +0100:
>
>>> static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
>>> {
>>> - BUG_ON(offs < 0x10);
>>> - if (offs < 0x3c)
>>> - return readl(smmu->regs[0] + off
Hi Joerg,
Joerg Roedel wrote @ Mon, 4 Feb 2013 20:53:32 +0100:
> > static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
> > {
> > - BUG_ON(offs < 0x10);
> > - if (offs < 0x3c)
> > - return readl(smmu->regs[0] + offs - 0x10);
> > - BUG_ON(offs < 0x1f0);
> > - if
On Thu, Jan 31, 2013 at 10:14:10AM +0200, Hiroshi Doyu wrote:
> drivers/iommu/tegra-smmu.c | 61
> ++--
> 1 file changed, 36 insertions(+), 25 deletions(-)
Okay, applied this patch to arm/tegra, but
> static inline u32 smmu_read(struct smmu_device *smm
Presently SMMU registers are located in discontiguous 3 blocks. They
are interleaved by MC registers. Ideally SMMU register blocks should
be in an independent one block, but it is too late to change this H/W
design. In the future Tegra chips over some generations, it is
expected that some of regist
On 01/29/2013 10:56 AM, Hiroshi Doyu wrote:
> Presently SMMU registers are located in discontiguous 3 blocks. They
> are interleaved by MC registers. Ideally SMMU register blocks should
> be in an independent one block, but it is too late to change this H/W
> design. In the future Tegra chips over
Presently SMMU registers are located in discontiguous 3 blocks. They
are interleaved by MC registers. Ideally SMMU register blocks should
be in an independent one block, but it is too late to change this H/W
design. In the future Tegra chips over some generations, it is
expected that some of regist
