Re: [RFC PATCH 4/6] iommu/arm-smmu: Add support for IOMMU_DOMAIN_DMA in SMMUv1/SMMUv2 driver

On 27/01/16 05:21, Anup Patel wrote: To allow use of large memory (> 4Gb) with 32bit devices we need to use some kind of iommu for such 32bit devices. This patch extends SMMUv1/SMMUv2 driver to support DMA domains which in-turn will allows us to use iommu based DMA mappings for 32bit devices.

Re: [RFC PATCH 5/6] iommu/arm-smmu: Option to treat instruction fetch as data read for SMMUv2

On 27/01/16 05:21, Anup Patel wrote: Currently, the SMMU driver by default provides unprivilege read-write permission in page table entries of stage1 page table. For SMMUv2 with aarch64 long descriptor format, a privilege instruction fetch will generate context fault. To allow privilege

Re: [RFC PATCH 3/6] of: iommu: Increment DT node refcount in of_iommu_set_ops()

On 27/01/16 05:21, Anup Patel wrote: We are saving pointer to iommu DT node in of_iommu_set_ops() hence we should increment DT node ref count. Oh man, shame on whoever wrote that code! :P Reviewed-by: Robin Murphy Signed-off-by: Anup Patel

Re: [PATCH 00/10] KVM PCIe/MSI passthrough on ARM/ARM64

On Tue, 2016-01-26 at 13:12 +, Eric Auger wrote: > This series addresses KVM PCIe passthrough with MSI enabled on ARM/ARM64. > It pursues the efforts done on [1], [2], [3]. It also aims at covering the > same need on some PowerPC platforms. >  > On x86 all accesses to the 1MB PA region

Re: [Patch v3 03/12] iommu/amd: move dte irq macro defitions to amd_iommu_types.h

Thanks a lot for your review, Zongshun. On 01/27/16 at 06:25pm, Wan Zongshun wrote: > > > Original Message > >These macro definitions are also needed by irq table copy function > >later, so move them to amd_iommu_types.h. > > Typo for your subject (defitions?). Yeah, this is

Re: [PATCH 00/10] KVM PCIe/MSI passthrough on ARM/ARM64

Hi Pavel, On 01/28/2016 08:13 AM, Pavel Fedin wrote: > Hello! > >> x86 isn't problem-free in this space. An x86 VM is going to know that >> the 0xfee0 address range is special, it won't be backed by RAM and >> won't be a DMA target, thus we'll never attempt to map it for an iova >> address.

Re: [PATCH v8 5/5] dts: mt8173: Add iommu/smi nodes for mt8173

On Tue, Jan 26, 2016 at 12:12 PM, Yong Wu wrote: > This patch add the iommu/larbs nodes for mt8173 > > Signed-off-by: Yong Wu Reviewed-by: Daniel Kurtz ___ iommu mailing list

Re: [PATCH v2 1/1] iommu/vt-d: use lo_hi_readq() / lo_hi_writeq()

On Thu, 2015-11-19 at 18:22 +0200, Andy Shevchenko wrote: > There is already helper functions to do 64-bit I/O on 32-bit machines > or buses, > thus we don't need to reinvent the wheel. > Any comment on this? > Signed-off-by: Andy Shevchenko > --- > Cahngelog

Re: [PATCH v8 3/5] memory: mediatek: Add SMI driver

On Tue, Jan 26, 2016 at 12:12 PM, Yong Wu wrote: > This patch add SMI(Smart Multimedia Interface) driver. This driver > is responsible to enable/disable iommu and control the power domain > and clocks of each local arbiter. > > Signed-off-by: Yong Wu >

Re: [Patch v3 06/12] iommu/amd: Clean up the useless IOMMU_PTE_U/IOMMU_PTE_FC

On 01/27/16 at 06:22pm, Wan Zongshun wrote: > > > Original Message > >In amd-vi spec bit[60:58] are only used to store the bit[14:12] of GCR3. > >No any other useage is found in several versions of amd-vi spec. So remove > >them in this patch. > > Also,this patch also made me

Re: [Patch v3 05/12] iommu/amd: change IOMMU_PTE_P to IOMMU_PTE_V

On 01/27/16 at 06:18pm, Wan Zongshun wrote: > > > Original Message > >In amd-vi spec the name of bit0 in DTE is V. But in code it's defined > >as IOMMU_PTE_P. Here change it to IOMMU_PTE_V to make it be consistent > >with spec. > > Hi, Baoquan > > This should be PR bit which

Re: [Patch v3 11/12] iommu/amd: No need to wait iommu completion if no dte irq entry change

On 01/27/16 at 07:03pm, Wan Zongshun wrote: > > > Original Message > > > > alias = amd_iommu_alias_table[devid]; > > table = irq_lookup_table[alias]; > >@@ -3688,7 +3688,7 @@ static struct irq_remap_table *get_irq_table(u16 > >devid, bool ioapic) > > /* Nothing

Re: [RFC PATCH 4/6] iommu/arm-smmu: Add support for IOMMU_DOMAIN_DMA in SMMUv1/SMMUv2 driver

On Thu, Jan 28, 2016 at 05:28:30PM +, Robin Murphy wrote: > On 27/01/16 05:21, Anup Patel wrote: > >To allow use of large memory (> 4Gb) with 32bit devices we need to use > >some kind of iommu for such 32bit devices. > > > >This patch extends SMMUv1/SMMUv2 driver to support DMA domains which >

RE: [RFC PATCH 4/6] iommu/arm-smmu: Add support for IOMMU_DOMAIN_DMA in SMMUv1/SMMUv2 driver

> -Original Message- > From: Robin Murphy [mailto:robin.mur...@arm.com] > Sent: 28 January 2016 22:59 > To: Anup Patel; Catalin Marinas; Joerg Roedel; Will Deacon; Sricharan R; Linux > IOMMU; Linux ARM Kernel > Cc: Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Device >

Re: [PATCH v3 1/3] iommu/io-pgtable: Add ARMv7 short descriptor support

On 27/01/16 01:16, Yong Wu wrote: On Tue, 2016-01-26 at 17:13 +, Robin Murphy wrote: Add a nearly-complete ARMv7 short descriptor implementation, omitting only a few legacy and CPU-centric aspects which shouldn't be necessary for IOMMU API use anyway. Signed-off-by: Yong Wu

Re: [Patch v3 11/12] iommu/amd: No need to wait iommu completion if no dte irq entry change

Original Message On 01/27/16 at 07:03pm, Wan Zongshun wrote: Original Message alias = amd_iommu_alias_table[devid]; table = irq_lookup_table[alias]; @@ -3688,7 +3688,7 @@ static struct irq_remap_table *get_irq_table(u16 devid, bool

RE: [RFC PATCH 5/6] iommu/arm-smmu: Option to treat instruction fetch as data read for SMMUv2

> -Original Message- > From: Robin Murphy [mailto:robin.mur...@arm.com] > Sent: 28 January 2016 22:41 > To: Anup Patel; Catalin Marinas; Joerg Roedel; Will Deacon; Robin Murphy; > Sricharan R; Linux IOMMU; Linux ARM Kernel > Cc: Mark Rutland; Device Tree; Scott Branden; Pawel Moll; Ian

Re: [Patch v3 05/12] iommu/amd: change IOMMU_PTE_P to IOMMU_PTE_V

Original Message On 01/27/16 at 06:18pm, Wan Zongshun wrote: Original Message In amd-vi spec the name of bit0 in DTE is V. But in code it's defined as IOMMU_PTE_P. Here change it to IOMMU_PTE_V to make it be consistent with spec. Hi, Baoquan This

Re: [Patch v3 05/12] iommu/amd: change IOMMU_PTE_P to IOMMU_PTE_V

On 01/29/16 at 10:55am, Wan Zongshun wrote: > > > Original Message > >On 01/27/16 at 06:18pm, Wan Zongshun wrote: > >> > >> > >> Original Message > >>>In amd-vi spec the name of bit0 in DTE is V. But in code it's defined > >>>as IOMMU_PTE_P. Here change it to