[PATCH 1/2] iommu/io-pgtable: Add MTK 4GB mode in Short-descriptor

Mediatek extend bit9 in the lvl1 and lvl2 pgtable descriptor of the Short-descriptor as the 4GB mode in which the dram size will be over 4GB. We add a special quirk for this MTK-4GB mode, And in the standard spec, Bit9 in the lvl1 is "IMPLEMENTATION DEFINED", while it's AP[2] in the lvl2,

[PATCH 2/2] iommu/mediatek: Add 4GB mode support

This patch add 4GB mode support for m4u. Signed-off-by: Yong Wu --- In this patch I use the global "max_pfn" to check whether the current dram size is over 4GB, I am not sure this is proper. If there is any other suggestions, please let me know. Thanks.

[PATCH 0/2] MT8173 IOMMU 4GB MODE SUPPORT

This patch-set add MTK 4GB mode support on the Short-Descriptor. MTK extend the bit9 of the standard pgtable descriptor as the 4GB mode. We add a special quirk for this. This two patches are based on Robin's Short-decriptor v3[1], MTK IOMMU v10[2] and Robin's "Rationalise quirk handling"[3].

Re: [PATCH V2] iommu/arm-smmu-v2: Add support for 16 bit VMID

On 02/23/2016 03:22 AM, Will Deacon wrote: Hi Tirumalesh, I still have some questions and comments about this. On Fri, Feb 19, 2016 at 10:33:33AM -0800, tchalama...@caviumnetworks.com wrote: From: Tirumalesh Chalamarla ARM-SMMUv2 supports upto 16 bit VMID.

[PATCH V3] iommu/arm-smmu-v2: Add support for 16 bit VMID

ARM-SMMUv2 supports upto 16 bit VMID. This patch enables 16 bit VMID when HW supports. Changes from V2: - Bug fix. - Removed not needed prints and comments. changes from V1: - Remove DT Property and enable 16 bit VMID if ID says. Signed-off-by: Tirumalesh Chalamarla

Re: [PATCH V4 5/6] perf/amd/iommu: Enable support for multiple IOMMUs

On 02/23/2016 12:24 PM, Alex Williamson wrote: On Tue, 23 Feb 2016 12:12:42 +0700 Suravee Suthikulpanit wrote: Hi On 02/22/2016 09:07 PM, Peter Zijlstra wrote: On Mon, Feb 22, 2016 at 03:00:31PM +0700, Suravee Suthikulpanit wrote: So I really don't have

Re: [PATCH V2] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

in Summary, if i change asid-base to cavium,asid-base and still use DT for supplying base value, is this a solution that will be accepted, of course i will do range check to see we are not supplying 16bit VMID for 8 bit systems even though the property now indicates Cavium only. Thanks,

Re: [PATCH V2] iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

On 02/23/2016 04:19 AM, Robin Murphy wrote: On 18/02/16 18:29, tchalama...@caviumnetworks.com wrote: From: Tirumalesh Chalamarla Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID namespaces; specifically within a given node SMMU0 and SMMU1

Re: [PATCH V4 0/6] perf/amd/iommu: Enable multi-IOMMU support

Hi Suravee, On Thu, Feb 11, 2016 at 04:15:21PM +0700, Suthikulpanit, Suravee wrote: > From: Suravee Suthikulpanit > > This patch series modifies the existing perf_event_amd_iommu driver > to support systems with multiple IOMMUs. It introduces new AMD IOMMU APIs, >

[PATCH V5 09/10] iommu/amd: Introduce amd_iommu_get_num_iommus()

This patch introduces amd_iommu_get_num_iommus(). This is intended for Perf AMD IOMMU driver. Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/perf/amd/iommu.h | 2 ++ drivers/iommu/amd_iommu_init.c| 7 ++- 2 files changed, 8

[PATCH V5 01/10] perf/amd/iommu: Misc fix up perf_iommu_read

This patch contains the follow minor fixup: * Fixed overflow handling since u64 delta would lose the MSB sign bit. * Remove unnecessary local64_set(). * Coding style and make use of GENMASK_ULL macro. Cc: Peter Zijlstra Cc: Borislav Petkov

[PATCH V5 08/10] perf/amd/iommu: Rename struct perf_amd_iommu to perf_iommu

This patch shortens the struct name perf_amd_iommu to perf_iommu since the old name is too long. The new name should be sufficient since the structure is only used within this file. We also clean up variable name for this structure in various functions. Cc: Borislav Petkov

[PATCH V5 00/10] perf/amd/iommu: Enable multi-IOMMU support

This is a two-part patch series: Part1: 1-4 : Introduce a workaround for the current AMD IOMMU perf initialization issue in some existing KV and CZ platforms, where it fails to write to IOMMU perf counter as reported by Andreas Hartmann here

[PATCH V5 04/10] perf/amd/iommu: Modify IOMMU API to allow specifying IOMMU index

The current amd_iommu_pc_set_reg_val() cann not support multi-IOMMU. So, this patch rename and modifies them to allow callers to specify IOMMU index. The function amd_iommu_pc_get_set_reg_val() is too confusing, and does not support multi-IOMMU. So, this patch breaks it down to

[PATCH V5 07/10] perf/amd/iommu: Clean up get_next_available_iommu_bnk_cntr

This patch cleans up the coding style of this function. This should not affect the logic and functionality. Cc: Borislav Petkov Signed-off-by: Suravee Suthikulpanit --- arch/x86/events/amd/iommu.c | 18 -- 1 file changed, 8

[PATCH V5 05/10] perf/amd/iommu: Declare pr_fmt and remove unnecessary pr_debug

This patch declare pr_fmt for perf/amd_iommu and remove unnecessary pr_debug. Cc: Borislav Petkov Signed-off-by: Suravee Suthikulpanit --- arch/x86/events/amd/iommu.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git

[PATCH V5 06/10] perf/amd/iommu: Clean up perf_iommu_enable_event

This patch cleans up: * Various bitwise operations in perf_iommu_enable_event * Make use macros BIT(x) This should not affect logic and functionality. Cc: Borislav Petkov Signed-off-by: Suravee Suthikulpanit --- arch/x86/events/amd/iommu.c |