On Thu, Dec 22, 2016 at 05:27:14PM +0100, Joerg Roedel wrote:
> Hi Bjorn,
>
> On Mon, Dec 19, 2016 at 03:20:44PM -0600, Bjorn Helgaas wrote:
> > I have some questions about dmar_init_reserved_ranges(). On systems
> > where CPU physical address space is not identity-mapped to PCI bus
> > address
Hi Eric,
On 12/13/2016 10:32 PM, Eric Auger wrote:
> In case the IOMMU does not bypass MSI transactions (typical
> case on ARM), we check all MSI controllers are IRQ remapping
> capable. If not the IRQ assignment may be unsafe.
>
> At this stage the arm-smmu-(v3) still advertise the
>
Hi Ashok,
On Thu, Dec 22, 2016 at 03:45:08PM -0800, Raj, Ashok wrote:
> Hi Bjorn
>
> None in the platform group say they know about this. So i'm fairly sure
> we don't do that on Intel hardware (x86).
I'm pretty sure there was once an x86 prototype for which PCI bus
addresses were not
Hi Bjorn
On Thu, Dec 22, 2016 at 02:28:03PM -0600, Bjorn Helgaas wrote:
> On Thu, Dec 22, 2016 at 05:27:14PM +0100, Joerg Roedel wrote:
> > Hi Bjorn,
> >
> > On Mon, Dec 19, 2016 at 03:20:44PM -0600, Bjorn Helgaas wrote:
> > > I have some questions about dmar_init_reserved_ranges(). On systems
Hi Bjorn
None in the platform group say they know about this. So i'm fairly sure
we don't do that on Intel hardware (x86).
I'm not sure about the usage, it appears maybe it was a hack
pre-virtualization for some direct access? (just wild guessing)
On Thu, Dec 22, 2016 at 03:32:38PM -0800,
Hi Diana,
On 22/12/2016 13:41, Diana Madalina Craciun wrote:
> Hi Eric,
>
> On 12/13/2016 10:32 PM, Eric Auger wrote:
>> In case the IOMMU does not bypass MSI transactions (typical
>> case on ARM), we check all MSI controllers are IRQ remapping
>> capable. If not the IRQ assignment may be
