Re: [PATCH V3 6/8] arm: dma-mapping: Reset the device's dma_ops

Hi Russell/Laurent/Robin, On 5/24/2017 4:12 AM, Russell King - ARM Linux wrote: > On Wed, May 24, 2017 at 12:46:51AM +0300, Laurent Pinchart wrote: >> Hi Russell, >> >> On Tuesday 23 May 2017 18:53:19 Russell King - ARM Linux wrote: >>> On Tue, May 23, 2017 at 05:55:57PM +0100, Robin Murphy

Re: [PATCH 1/2] staging: fsl-dpaa2/eth: Fix address translations

Hi Ioana, Debatable nit inline. On 05/24/2017 03:13 PM, Ioana Radulescu wrote: > Use the correct mechanisms for translating a DMA-mapped IOVA > address into a virtual one. Without this fix, once SMMU is > enabled on Layerscape platforms, the Ethernet driver throws > IOMMU translation faults. > >

Re: [PATCH V3 6/8] arm: dma-mapping: Reset the device's dma_ops

Hello, On Wednesday 24 May 2017 16:01:45 Sricharan R wrote: > On 5/24/2017 4:12 AM, Russell King - ARM Linux wrote: > > On Wed, May 24, 2017 at 12:46:51AM +0300, Laurent Pinchart wrote: > >> On Tuesday 23 May 2017 18:53:19 Russell King - ARM Linux wrote: > >>> On Tue, May 23, 2017 at 05:55:57PM

Re: [PATCH V3 6/8] arm: dma-mapping: Reset the device's dma_ops

Hi Laurent, On 5/24/2017 4:56 PM, Laurent Pinchart wrote: > Hello, > > On Wednesday 24 May 2017 16:01:45 Sricharan R wrote: >> On 5/24/2017 4:12 AM, Russell King - ARM Linux wrote: >>> On Wed, May 24, 2017 at 12:46:51AM +0300, Laurent Pinchart wrote: On Tuesday 23 May 2017 18:53:19 Russell

[PATCH] iommu/amd: constify irq_domain_ops

struct irq_domain_ops is not modified, so it can be made const. Signed-off-by: Tobias Klauser --- drivers/iommu/amd_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index

[PATCH 2/2] staging: fsl-dpaa2/eth: Map Tx buffers as bidirectional

WRIOP hardware may need to write to the hardware annotation area of Tx buffers (e.g. frame status bits) and also to the data area (e.g. L4 checksum in frame header). Map these buffers as DMA_BIDIRECTIONAL, otherwise the write transaction through SMMU will not be allowed. Signed-off-by: Nipun

[PATCH 1/2] staging: fsl-dpaa2/eth: Fix address translations

Use the correct mechanisms for translating a DMA-mapped IOVA address into a virtual one. Without this fix, once SMMU is enabled on Layerscape platforms, the Ethernet driver throws IOMMU translation faults. Signed-off-by: Nipun Gupta Signed-off-by: Ioana Radulescu

[PATCH 0/7] Add PCI ATS support to SMMUv3

PCIe devices can implement their own TLB, named Address Translation Cache (ATC). In order to support Address Translation Service (ATS), the following changes are needed in software: * Enable ATS on endpoints when the system supports it. Both PCI root complex and associated SMMU must implement

[PATCH 3/7] iommu/of: Check ATS capability in root complex nodes

The PCI root complex node in DT has a property indicating whether it supports ATS. Store this bit in the IOMMU fwspec when initializing a device, so it can be accessed later by an IOMMU driver. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/of_iommu.c | 8

[PATCH 1/7] PCI: Move ATS declarations outside of CONFIG_PCI

Currently ATS helpers like pci_enable_ats are only defined when CONFIG_PCI is enabled. The ARM SMMU driver might get built with CONFIG_PCI disabled. It would thus have to wrap any use of ATS helpers around #ifdef CONFIG_PCI, which isn't ideal. A nicer solution is to always define these helpers.

[PATCH 2/7] dt-bindings: PCI: Describe ATS property for root complex nodes

Address Translation Service (ATS) is an extension to PCIe allowing endpoints to manage their own IOTLB, called Address Translation Cache (ATC). Instead of having every memory transaction processed by the IOMMU, the endpoint can first send an Address Translation Requests for an IOVA, obtain the

[PATCH 5/7] iommu/arm-smmu-v3: Link domains and devices

When removing a mapping from a domain, we need to send an invalidation to all devices that might have stored it in their Address Translation Cache (ATC). In addition with SVM, we'll need to invalidate context descriptors of all devices attached to a domain. Maintain a list of devices in each

[PATCH 7/7] iommu/arm-smmu-v3: Disable tagged pointers

The ARM architecture has a "Top Byte Ignore" (TBI) option that makes the MMU mask out bits [63:56] of an address, allowing a userspace application to store data in its pointers. This option is incompatible with PCI ATS. If TBI is enabled in the SMMU and userspace triggers DMA transactions on

[PATCH 4/7] ACPI/IORT: Check ATS capability in root complex nodes

Root complex node in IORT has a bit telling whether it supports ATS or not. Store this bit in the IOMMU fwspec when setting up a device, so it can be accessed later by an IOMMU driver. Signed-off-by: Jean-Philippe Brucker --- drivers/acpi/arm64/iort.c | 10

[PATCH 6/7] iommu/arm-smmu-v3: Add support for PCI ATS

PCIe devices can implement their own TLB, named Address Translation Cache (ATC). Enable Address Translation Service (ATS) for devices that support it and send them invalidation requests whenever we invalidate the IOTLBs. Range calculation - The invalidation packet itself is a

Re: [PATCH 1/2] PCI: Save properties required to handle FLR for replay purposes.

On Tue, May 23, 2017 at 03:33:22PM -0500, Bjorn Helgaas wrote: > On Wed, May 10, 2017 at 11:39:02AM -0700, Ashok Raj wrote: > > From: CQ Tang > > > > Requires: https://patchwork.kernel.org/patch/9593891 > > I'm not sure what the status of the patch above is. I acked it, but