Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

On 2017/5/17 18:13, Shameerali Kolothum Thodi wrote: #ifdef CONFIG_ACPI +static void acpi_smmu_get_options(u32 model, struct arm_smmu_device +*smmu) { + if (model == ACPI_IORT_SMMU_CAVIUM_CN99XX) + smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY; > HiSIlicon hip06/07 boards

Re: [PATCH v7 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

On 30/05/2017 13:03, Geetha sowjanya wrote: From: Geetha Sowjanya Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq separate irq lines lines for gerror, eventq and cmdq-sync. This patch addresses the issue by checking if any

Re: [PATCH 2/7] dt-bindings: PCI: Describe ATS property for root complex nodes

On 05/06/17 18:20, Rob Herring wrote: > On Thu, Jun 01, 2017 at 01:28:01PM +0100, Jean-Philippe Brucker wrote: >> On 31/05/17 18:23, Rob Herring wrote: >>> On Wed, May 24, 2017 at 07:01:38PM +0100, Jean-Philippe Brucker wrote: Address Translation Service (ATS) is an extension to PCIe allowing

Re: [RFCv2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

On Wed, May 31, 2017 at 03:32:13PM +0100, shameer wrote: > The HiSilicon erratum 161010801 describes the limitation of HiSilicon > platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. > > On these platforms GICv3 ITS translator is presented with the deviceID > by extending the

Re: [RFCv2 1/2] acpi:iort: Add new helper function to retrieve ITS base addr from dev IORT node

On Wed, May 31, 2017 at 03:32:12PM +0100, shameer wrote: > This provides a helper function to find and retrieve the ITS > base address from the ID mappings array reference of a device > IORT node(if any). > > This is used in the subsequent patch to retrieve the ITS base > address associated with

Re: 回复： Alibaba-kernel

On Tue, 6 Jun 2017 13:25:00 +0800 "若翾" wrote: > Hi，Jacob， > Thank you for your reply， > alibaba in San Mateo ， > Do you have a WeChat? You can add me > WeChat15900779704 > I see, I am not planning to relocate at the moment but I will keep it in mind. Thanks, > > > > >

RE: [RFCv2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

Hi Lorenzo, > -Original Message- > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] > Sent: Tuesday, June 06, 2017 2:56 PM > To: Shameerali Kolothum Thodi > Cc: marc.zyng...@arm.com; sudeep.ho...@arm.com; will.dea...@arm.com; > robin.mur...@arm.com; hanjun@linaro.org;

RE: [RFCv2 1/2] acpi:iort: Add new helper function to retrieve ITS base addr from dev IORT node

> -Original Message- > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] > Sent: Tuesday, June 06, 2017 3:10 PM > To: Shameerali Kolothum Thodi > Cc: marc.zyng...@arm.com; sudeep.ho...@arm.com; will.dea...@arm.com; > robin.mur...@arm.com; hanjun@linaro.org; Gabriele Paoloni;

Re: [PATCH v1 3/3] iommu/amd: Optimize the IOMMU queue flush

Hey Tom, On Mon, Jun 05, 2017 at 02:52:35PM -0500, Tom Lendacky wrote: > After reducing the amount of MMIO performed by the IOMMU during operation, > perf data shows that flushing the TLB for all protection domains during > DMA unmapping is a performance issue. It is not necessary to flush the >

Re: [PATCH 02/12] intel-ipu3: mmu: implement driver

Hi Yong, Tuukka, +CC IOMMU ML and Joerg. (Technically you should resend this patch including them.) On Tue, Jun 6, 2017 at 5:39 AM, Yong Zhi wrote: > From: Tuukka Toivonen > > This driver translates Intel IPU3 internal virtual > address to

[PATCH v2 1/2] acpica: iort: Update SMMUv3 header for proximity domain mapping

ARM IORT specification (rev. C) has added two new fields to define proximity domain for the SMMUv3 node in the IORT table. Proximity Domain Valid: Set to 1 if the value provided in the Proximity Domain field is valid. Set to 0 otherwise. Proximity domain: If the Proximity

[PATCH v2 0/2] acpi/iort, numa: Add numa node mapping for smmuv3 devices

ARM IORT specification(rev. C) has added provision to define proximity domain in SMMUv3 IORT table. Adding required code to parse Proximity domain and set numa_node of smmv3 platform devices. Signed-off-by: Ganapatrao Kulkarni v2: - Changed as per Lorenzo

[PATCH v2 2/2] acpi/iort: numa: Add numa node mapping for smmuv3 devices

Add code to parse proximity domain in SMMUv3 IORT table to set numa node mapping for smmuv3 devices. Signed-off-by: Ganapatrao Kulkarni --- drivers/acpi/arm64/iort.c | 20 1 file changed, 20 insertions(+) diff --git

RE: [PATCH v1 3/3] iommu/amd: Optimize the IOMMU queue flush

>-Original Message- >From: Lendacky, Thomas >Sent: Tuesday, June 06, 2017 1:23 AM >To: iommu@lists.linux-foundation.org >Cc: Nath, Arindam ; Joerg Roedel >; Duran, Leo ; Suthikulpanit, >Suravee

Re: [PATCH v1 3/3] iommu/amd: Optimize the IOMMU queue flush

On 6/6/2017 7:05 AM, Joerg Roedel wrote: Hey Tom, Hi Joerg, On Mon, Jun 05, 2017 at 02:52:35PM -0500, Tom Lendacky wrote: After reducing the amount of MMIO performed by the IOMMU during operation, perf data shows that flushing the TLB for all protection domains during DMA unmapping is a