On Wed, 30 May 2018 12:53:53 +0100
Jean-Philippe Brucker wrote:
> On 30/05/18 04:45, Tian, Kevin wrote:
> >> On SMMUv3 the minimum alignment for base_ptr is 64 bytes, so
> >> a
> guest
> >> under a vSMMU might pass a pointer that's not aligned on 4k.
> >>
> > PASID
Hi Christoph,
For patches 1-4:
Reviewed-by: Paul Burton
Comment below for this patch though.
On Fri, May 25, 2018 at 11:20:51AM +0200, Christoph Hellwig wrote:
> diff --git a/arch/mips/cavium-octeon/dma-octeon.c
> b/arch/mips/cavium-octeon/dma-octeon.c
> index e5d00c79bd26..1e68636c9137
From: owner-linux...@kvack.org [mailto:owner-linux...@kvack.org] On Behalf Of
Michal Hocko
Sent: Monday, May 28, 2018 9:38 PM
> > In my opinion, originally there shouldn't be such many wrong
> > combinations of these bottom 3 bits. For any user, whether or
> > driver and fs, they should make a
Hi,
On 05/30/2018 12:20 AM, Jacob Pan wrote:
> On Mon, 14 May 2018 15:43:54 +0800
> Lu Baolu wrote:
>
>> Hi,
>>
>> On 05/12/2018 04:54 AM, Jacob Pan wrote:
>>> When IO page faults are reported outside IOMMU subsystem, the page
>>> request handler may fail for various reasons. E.g. a guest
Hi Robin,
On Mon, May 21, 2018 at 7:12 PM, Robin Murphy wrote:
> On 22/03/18 10:22, Vivek Gautam wrote:
>>
>> This series provides the support for turning on the arm-smmu's
>> clocks/power domains using runtime pm. This is done using the
>> recently introduced device links patches, which lets
From: Thierry Reding
An unfortunate interaction between the 32-bit ARM DMA/IOMMU mapping code
and Tegra SMMU driver changes to support IOMMU groups introduced a boot-
time regression on Tegra124. This was caught very late because none of
the standard configurations that are tested on Tegra
From: Thierry Reding
Implement this function to enable drivers from detaching from any IOMMU
domains that architecture code might have attached them to so that they
can take exclusive control of the IOMMU via the IOMMU API.
Signed-off-by: Thierry Reding
---
Changes in v3:
- make API 32-bit ARM
On Wed, May 30, 2018 at 09:02:13AM +, Huaisheng HS1 Ye wrote:
>
> I don't quite understand that. I think those, mostly drivers, need to
> get the correct zone they want. ZONE_DMA32 is an example, if drivers can be
> satisfied with a low mem zone, why they mark the gfp flags as
>
On Wed 30-05-18 09:02:13, Huaisheng HS1 Ye wrote:
> From: owner-linux...@kvack.org [mailto:owner-linux...@kvack.org] On Behalf Of
> Michal Hocko
> Sent: Monday, May 28, 2018 9:38 PM
> > > In my opinion, originally there shouldn't be such many wrong
> > > combinations of these bottom 3 bits. For
On 30/05/18 09:03, Thierry Reding wrote:
From: Thierry Reding
Implement this function to enable drivers from detaching from any IOMMU
domains that architecture code might have attached them to so that they
can take exclusive control of the IOMMU via the IOMMU API.
Signed-off-by: Thierry
From: Thierry Reding
Depending on the kernel configuration, early ARM architecture setup code
may have attached the GPU to a DMA/IOMMU mapping that transparently uses
the IOMMU to back the DMA API. Tegra requires special handling for IOMMU
backed buffers (a special bit in the GPU's MMU page
On 30/05/18 09:03, Thierry Reding wrote:
From: Thierry Reding
Depending on the kernel configuration, early ARM architecture setup code
may have attached the GPU to a DMA/IOMMU mapping that transparently uses
the IOMMU to back the DMA API. Tegra requires special handling for IOMMU
backed
On 30/05/18 04:45, Tian, Kevin wrote:
>> On SMMUv3 the minimum alignment for base_ptr is 64 bytes, so a
guest
>> under a vSMMU might pass a pointer that's not aligned on 4k.
>>
> PASID table pointer for VT-d is 4K aligned.
>> Maybe this information could be part of the
On 30/05/18 14:41, Thierry Reding wrote:
On Wed, May 30, 2018 at 02:30:51PM +0100, Robin Murphy wrote:
On 30/05/18 14:00, Thierry Reding wrote:
On Wed, May 30, 2018 at 11:30:25AM +0100, Robin Murphy wrote:
On 30/05/18 09:03, Thierry Reding wrote:
From: Thierry Reding
Depending on the
On Wed, May 30, 2018 at 10:59:30AM +0100, Robin Murphy wrote:
> On 30/05/18 09:03, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Implement this function to enable drivers from detaching from any IOMMU
> > domains that architecture code might have attached them to so that they
> > can
On Wed, May 30, 2018 at 02:54:46PM +0200, Thierry Reding wrote:
> On Wed, May 30, 2018 at 10:59:30AM +0100, Robin Murphy wrote:
> > On 30/05/18 09:03, Thierry Reding wrote:
> > > From: Thierry Reding
> > >
> > > Implement this function to enable drivers from detaching from any IOMMU
> > >
On 30/05/18 14:00, Thierry Reding wrote:
On Wed, May 30, 2018 at 11:30:25AM +0100, Robin Murphy wrote:
On 30/05/18 09:03, Thierry Reding wrote:
From: Thierry Reding
Depending on the kernel configuration, early ARM architecture setup code
may have attached the GPU to a DMA/IOMMU mapping that
On Wed, May 30, 2018 at 02:30:51PM +0100, Robin Murphy wrote:
> On 30/05/18 14:00, Thierry Reding wrote:
> > On Wed, May 30, 2018 at 11:30:25AM +0100, Robin Murphy wrote:
> > > On 30/05/18 09:03, Thierry Reding wrote:
> > > > From: Thierry Reding
> > > >
> > > > Depending on the kernel
On 30/05/18 14:12, Thierry Reding wrote:
On Wed, May 30, 2018 at 02:54:46PM +0200, Thierry Reding wrote:
On Wed, May 30, 2018 at 10:59:30AM +0100, Robin Murphy wrote:
On 30/05/18 09:03, Thierry Reding wrote:
From: Thierry Reding
Implement this function to enable drivers from detaching from
On Wed, May 30, 2018 at 11:30:25AM +0100, Robin Murphy wrote:
> On 30/05/18 09:03, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Depending on the kernel configuration, early ARM architecture setup code
> > may have attached the GPU to a DMA/IOMMU mapping that transparently uses
> > the
From: Thierry Reding
An unfortunate interaction between the 32-bit ARM DMA/IOMMU mapping code
and Tegra SMMU driver changes to support IOMMU groups introduced a boot-
time regression on Tegra124. This was caught very late because none of
the standard configurations that are tested on Tegra
From: Thierry Reding
Depending on the kernel configuration, early ARM architecture setup code
may have attached the GPU to a DMA/IOMMU mapping that transparently uses
the IOMMU to back the DMA API. Tegra requires special handling for IOMMU
backed buffers (a special bit in the GPU's MMU page
From: Thierry Reding
Instead of setting the DMA ops pointer to NULL, set the correct,
non-IOMMU ops depending on the device's coherency setting.
Signed-off-by: Thierry Reding
---
Changes in v4:
- new patch to fix existing arm_iommu_detach_device() to do what we need
arch/arm/mm/dma-mapping.c
On Wed, May 30, 2018 at 02:42:50PM +0100, Robin Murphy wrote:
> On 30/05/18 14:12, Thierry Reding wrote:
> > On Wed, May 30, 2018 at 02:54:46PM +0200, Thierry Reding wrote:
> > > On Wed, May 30, 2018 at 10:59:30AM +0100, Robin Murphy wrote:
> > > > On 30/05/18 09:03, Thierry Reding wrote:
> > > >
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