Re: [PATCH 4/6] dma-mapping: merge direct and noncoherent ops

Hi Christoph, On Fri, 14 Sep 2018, Christoph Hellwig wrote: > All the cache maintainance is already stubbed out when not enabled, > but merging the two allows us to nicely handle the case where > cache maintainance is required for some devices, but not others. FYI, you commit bc3ec75de545

Re: [PATCH 4/6] dma-mapping: merge direct and noncoherent ops

On Wed, 31 Oct 2018, Maciej W. Rozycki wrote: > > All the cache maintainance is already stubbed out when not enabled, > > but merging the two allows us to nicely handle the case where > > cache maintainance is required for some devices, but not others. > > FYI, you commit bc3ec75de545

Re: [PATCH 4/6] dma-mapping: merge direct and noncoherent ops

Can you send me your .config? ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu

[PATCH RFC] dma-direct: do not allocate a single page from CMA area

The addresses within a single page are always contiguous, so it's not so necessary to allocate one single page from CMA area. Since the CMA area has a limited predefined size of space, it might run out of space in some heavy use case, where there might be quite a lot CMA pages being allocated for

[PATCH v2 0/5] Add Tegra194 Dual ARM SMMU driver

NVIDIA's Xavier (Tegra194) SOC has three ARM SMMU(MMU-500) instances. Two of the SMMU instances are used to interleave IOVA accesses across them. The IOVA accesses from HW devices are interleaved across these two SMMU instances and they need to be programmed identical. The existing ARM SMMU

[PATCH v2 1/5] iommu/arm-smmu: rearrange arm-smmu.c code

Rearrange arm-smmu.c code into arm-smmu-common.h, arm-smmu-common.c and arm-smmu.c. This patch rearranges the arm-smmu.c code to allow sharing the ARM SMMU driver code with dual ARM SMMU based Tegra194 SMMU driver. Signed-off-by: Krishna Reddy --- drivers/iommu/arm-smmu-common.c | 1922

[PATCH v2 2/5] iommu/arm-smmu: Prepare fault, probe, sync functions for sharing code

Prepare fault handling, probe and tlb sync functions to allow sharing code between ARM SMMU driver and Tegra194 SMMU driver. Signed-off-by: Krishna Reddy --- drivers/iommu/arm-smmu-common.c | 53 +++-- drivers/iommu/arm-smmu.c| 42

[PATCH v2 5/5] arm64: tegra: Add SMMU nodes to Tegra194 device tree

Add SMMU nodes and dma-ranges to Tegra194 device tree. Tegra194 has three ARM SMMU Instances. Two of them are used together to access IOVA interleaved. The third one is used as regular ARM SMMU. Signed-off-by: Krishna Reddy --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 148

[PATCH v2 4/5] arm64: defconfig: Enable ARM_SMMU_TEGRA

Enabling CONFIG_ARM_SMMU_TEGRA that is used by Tegra194 SOC. Signed-off-by: Krishna Reddy --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4b38444..d875f64 100644 ---

[PATCH v2 3/5] iommu/tegra194_smmu: Add Tegra194 SMMU driver

Tegra194 SMMU driver supports Dual ARM SMMU configuration supported in Tegra194 SOC. The IOVA accesses from HW devices are interleaved across two ARM SMMU devices. Signed-off-by: Krishna Reddy --- drivers/iommu/Kconfig | 10 +++ drivers/iommu/Makefile| 1 +

Re: [PATCH 4/6] dma-mapping: merge direct and noncoherent ops

On Wed, Oct 31, 2018 at 08:50:53PM +, Maciej W. Rozycki wrote: > On Wed, 31 Oct 2018, Christoph Hellwig wrote: > > > Can you send me your .config? > > Sure, attached. > > This is an updated 4.19 defconfig I was going to submit as I tripped over > this problem, so just rename it to

Re: [PATCH v3 1/1] iommu/arm-smmu-v3: eliminate a potential memory corruption on hi1620 and earlier

On 31/10/2018 04:02, Zhen Lei wrote: The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon expands the next 4 bytes to carry some IMPDEF information. That means, total 8 bytes data will be written to MSIAddress each time. MSIAddr: |4bytes|4bytes| |