Re: use generic DMA mapping code in powerpc V4

Next step: c1bfcad4b0cf38ce5b00f7ad880d3a13484c123a (dma-mapping, powerpc: simplify the arch dma_set_mask override) Result: No problems with the PASEMI onboard ethernet and with booting the X5000 (P5020 board). -- Christian On 09 December 2018 at 3:20PM, Christian Zigotzky wrote: Next

[PATCH v6 17/21] iommu/tegra: gart: Don't use managed resources

GART is a part of the Memory Controller driver that is always built-in, hence there is no benefit from the use of managed resources. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding --- drivers/iommu/tegra-gart.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff

[PATCH v6 21/21] iommu/tegra: gart: Perform code refactoring

Removed redundant safety-checks in the code and some debug code that isn't actually very useful for debugging, like enormous pagetable dump on each fault. The majority of the changes are code reshuffling, variables/whitespaces clean up and removal of debug messages that duplicate messages of the

[PATCH v6 20/21] iommu/tegra: gart: Simplify clients-tracking code

GART is a simple IOMMU provider that has single address space. There is no need to setup global clients list and manage it for tracking of the active domain, hence lot's of code could be safely removed and replaced with a simpler alternative. Signed-off-by: Dmitry Osipenko Acked-by: Thierry

[PATCH v6 18/21] iommu/tegra: gart: Prepend error/debug messages with "gart:"

GART became a part of Memory Controller, hence now the drivers device is Memory Controller and not GART. As a result all printed messages are prepended with the "tegra-mc 7000f000.memory-controller:", so let's prepend GART's messages with "gart:" in order to differentiate them from the MC.

[PATCH v6 19/21] iommu/tegra: gart: Don't detach devices from inactive domains

There could be unlimited number of allocated domains, but only one domain can be active at a time. Hence devices must be detached only from the active domain. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding --- drivers/iommu/tegra-gart.c | 8 +--- 1 file changed, 5 insertions(+), 3

Re: use generic DMA mapping code in powerpc V4

Next step: 602307b034734ce77a05da4b99333a2eaf6b6482 (powerpc/fsl_pci: simplify fsl_pci_dma_set_mask) git checkout 602307b034734ce77a05da4b99333a2eaf6b6482 The PASEMI onboard ethernet works and the X5000 boots. -- Christian On 08 December 2018 at 2:47PM, Christian Zigotzky wrote: Next step:

[PATCH v6 04/21] iommu: Introduce iotlb_sync_map callback

Introduce iotlb_sync_map() callback that is invoked in the end of iommu_map(). This new callback allows IOMMU drivers to avoid syncing after mapping of each contiguous chunk and sync only when the whole mapping is completed, optimizing performance of the mapping operation. Signed-off-by: Dmitry

[PATCH v6 00/21] IOMMU: Tegra GART driver clean up and optimization

Hello, This patch-series integrates the GART (IOMMU) driver with the Memory Controller driver, that allows to report the name of a faulty memory client on GART page fault. A major code clean up and performance optimization is performed in this series as well. Changelog: v6: v5 that is re-based

[PATCH v6 01/21] iommu/tegra: gart: Remove pr_fmt and clean up includes

Remove unneeded headers inclusion and sort the headers in alphabet order. Remove pr_fmt macro since there is no pr_*() in the code and it doesn't affect dev_*() functions. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding --- drivers/iommu/tegra-gart.c | 17 + 1 file

[PATCH v6 03/21] iommu/tegra: gart: Ignore devices without IOMMU phandle in DT

GART can't handle all devices, hence ignore devices that aren't related to GART. IOMMU phandle must be explicitly assign to devices in the device tree. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding --- drivers/iommu/tegra-gart.c | 14 +- 1 file changed, 13 insertions(+),

Re: [RFC PATCH 0/6] Auxiliary IOMMU domains and Arm SMMUv3

Hi Joerg, On 12/7/18 6:29 PM, 'j...@8bytes.org' wrote: Hi, On Mon, Nov 26, 2018 at 07:29:45AM +, Tian, Kevin wrote: btw Baolu just reminded me one thing which is worthy of noting here. 'primary' vs. 'aux' concept makes sense only when we look from a device p.o.v. That binding relationship

[PATCH v6 08/12] iommu/vt-d: Pass pasid table to context mapping

So that the pasid related info, such as the pasid table and the maximum of pasid could be used during setting up scalable mode context. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Cc: Sanjay Kumar Signed-off-by: Lu Baolu Reviewed-by: Ashok Raj Reviewed-by: Kevin Tian ---

[PATCH v6 02/12] iommu/vt-d: Manage scalalble mode PASID tables

In scalable mode, pasid structure is a two level table with a pasid directory table and a pasid table. Any pasid entry can be identified by a pasid value in below way. 1 9 6 5 0 .---.---. | PASID| |

[PATCH v6 05/12] iommu/vt-d: Reserve a domain id for FL and PT modes

Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid entry for first-level or pass-through translation should be programmed with a domain id different from those used for second-level or nested translation. It is recommended that software could use a same domain id for all first-only and

[PATCH v6 12/12] iommu/vt-d: Remove deferred invalidation

Deferred invalidation is an ECS specific feature. It will not be supported when IOMMU works in scalable mode. As we deprecated the ECS support, remove deferred invalidation and cleanup the code. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Cc: Sanjay Kumar Signed-off-by: Lu Baolu

[PATCH v6 10/12] iommu/vt-d: Add first level page table interface

This adds an interface to setup the PASID entries for first level page table translation. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Signed-off-by: Sanjay Kumar Signed-off-by: Liu Yi L Signed-off-by: Lu Baolu Reviewed-by: Ashok Raj --- drivers/iommu/intel-pasid.c | 80

[PATCH v6 03/12] iommu/vt-d: Move page table helpers into header

So that they could also be used in other source files. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Cc: Sanjay Kumar Signed-off-by: Lu Baolu Reviewed-by: Ashok Raj Reviewed-by: Kevin Tian --- drivers/iommu/intel-iommu.c | 43 -

[PATCH v6 07/12] iommu/vt-d: Setup pasid entry for RID2PASID support

when the scalable mode is enabled, there is no second level page translation pointer in the context entry any more (for DMA request without PASID). Instead, a new RID2PASID field is introduced in the context entry. Software can choose any PASID value to set RID2PASID and then setup the translation

[PATCH v6 06/12] iommu/vt-d: Add second level page table interface

This adds the interfaces to setup or tear down the structures for second level page table translations. This includes types of second level only translation and pass through. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Signed-off-by: Sanjay Kumar Signed-off-by: Liu Yi L Signed-off-by: Lu

[PATCH v6 00/12] iommu/vt-d: Add scalable mode support

Hi, Intel vt-d rev3.0 [1] introduces a new translation mode called 'scalable mode', which enables PASID-granular translations for first level, second level, nested and pass-through modes. The vt-d scalable mode is the key ingredient to enable Scalable I/O Virtualization (Scalable IOV) [2] [3],

[PATCH v6 11/12] iommu/vt-d: Shared virtual address in scalable mode

This patch enables the current SVA (Shared Virtual Address) implementation to work in the scalable mode. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Signed-off-by: Sanjay Kumar Signed-off-by: Liu Yi L Signed-off-by: Lu Baolu Reviewed-by: Ashok Raj --- drivers/iommu/intel-iommu.c | 38

[PATCH v6 09/12] iommu/vt-d: Setup context and enable RID2PASID support

This patch enables the translation for requests without PASID in the scalable mode by setting up the root and context entries. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Signed-off-by: Sanjay Kumar Signed-off-by: Liu Yi L Signed-off-by: Lu Baolu Reviewed-by: Ashok Raj ---

RE: [RFC PATCH 0/6] Auxiliary IOMMU domains and Arm SMMUv3

> From: 'j...@8bytes.org' [mailto:j...@8bytes.org] > Sent: Friday, December 7, 2018 6:29 PM > > Hi, > > On Mon, Nov 26, 2018 at 07:29:45AM +, Tian, Kevin wrote: > > btw Baolu just reminded me one thing which is worthy of noting here. > > 'primary' vs. 'aux' concept makes sense only when we

[PATCH v2 1/2] swiotlb: add debugfs to track swiotlb buffer usage

The device driver will not be able to do dma operations once swiotlb buffer is full, either because the driver is using so many IO TLB blocks inflight, or because there is memory leak issue in device driver. To export the swiotlb buffer usage via debugfs would help the user estimate the size of

[PATCH v2 2/2] swiotlb: checking whether swiotlb buffer is full with io_tlb_used

This patch uses io_tlb_used to help check whether swiotlb buffer is full. io_tlb_used is no longer used for only debugfs. It is also used to help optimize swiotlb_tbl_map_single(). Suggested-by: Joe Jin Signed-off-by: Dongli Zhang --- kernel/dma/swiotlb.c | 10 -- 1 file changed, 4

[PATCH v6 2/3] iommu/io-pgtable-arm-v7s: Request DMA32 memory, and improve debugging

IOMMUs using ARMv7 short-descriptor format require page tables (level 1 and 2) to be allocated within the first 4GB of RAM, even on 64-bit systems. For level 1/2 pages, ensure GFP_DMA32 is used if CONFIG_ZONE_DMA32 is defined (e.g. on arm64 platforms). For level 2 pages, allocate a slab cache in

[PATCH v6 1/3] mm: Add support for kmem caches in DMA32 zone

IOMMUs using ARMv7 short-descriptor format require page tables to be allocated within the first 4GB of RAM, even on 64-bit systems. On arm64, this is done by passing GFP_DMA32 flag to memory allocation functions. For IOMMU L2 tables that only take 1KB, it would be a waste to allocate a full page

[PATCH v6 3/3] mm: Add /sys/kernel/slab/cache/cache_dma32

A previous patch in this series adds support for SLAB_CACHE_DMA32 kmem caches. This adds the corresponding /sys/kernel/slab/cache/cache_dma32 entries, and fixes slabinfo tool. Cc: sta...@vger.kernel.org Signed-off-by: Nicolas Boichat --- There were different opinions on whether this sysfs entry

[PATCH v6 0/3] iommu/io-pgtable-arm-v7s: Use DMA32 zone for page tables

This is a follow-up to the discussion in [1], [2]. IOMMUs using ARMv7 short-descriptor format require page tables (level 1 and 2) to be allocated within the first 4GB of RAM, even on 64-bit systems. For L1 tables that are bigger than a page, we can just use __get_free_pages with GFP_DMA32 (on

[PATCH v6 05/21] iommu/tegra: gart: Optimize mapping / unmapping performance

Currently GART writes one page entry at a time. More optimal would be to aggregate the writes and flush BUS buffer in the end, this gives map/unmap 10-40% performance boost (depending on size of mapping) in comparison to flushing after each page entry update. Signed-off-by: Dmitry Osipenko

[PATCH v6 08/21] memory: tegra: Don't invoke Tegra30+ specific memory timing setup on Tegra20

This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory timings for RAM code 0 registered" warning message during of kernels boot-up on Tegra20. Fixes: a8d502fd3348 ("memory: tegra: Squash tegra20-mc into common tegra-mc driver") Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter

[PATCH v6 09/21] memory: tegra: Adapt to Tegra20 device-tree binding changes

The tegra20-mc device-tree binding has been changed, GART has been squashed into Memory Controller and now the clock property is mandatory for Tegra20, the DT compatible has been changed as well. Adapt driver to the DT changes. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/mc.c | 21

[PATCH v6 06/21] dt-bindings: memory: tegra: Squash tegra20-gart into tegra20-mc

Splitting GART and Memory Controller wasn't a good decision that was made back in the day. Given that the GART driver wasn't ever been used by anything in the kernel, we decided that it will be better to correct the mistakes of the past and merge two bindings into a single one. As a result there

[PATCH v6 13/21] iommu/tegra: gart: Integrate with Memory Controller driver

The device-tree binding has been changed. There is no separate GART device anymore, it is squashed into the Memory Controller. Integrate GART module with the MC in a way it is done for the SMMU of Tegra30+. Signed-off-by: Dmitry Osipenko --- drivers/iommu/Kconfig | 1 +

[PATCH v6 16/21] iommu/tegra: gart: Allow only one active domain at a time

GART has a single address space that is shared by all devices, hence only one domain could be active at a time. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding --- drivers/iommu/tegra-gart.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/iommu/tegra-gart.c

[PATCH v6 12/21] memory: tegra: Use relaxed versions of readl/writel

There is no need for inserting of memory barriers to access registers of Memory Controller. Hence use the relaxed versions of the accessors. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/mc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH v6 14/21] iommu/tegra: gart: Fix spinlock recursion

Fix spinlock recursion bug that happens on IOMMU domain destruction if any of the allocated domains have devices attached to them. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding --- drivers/iommu/tegra-gart.c | 24 1 file changed, 16 insertions(+), 8

[PATCH v6 15/21] iommu/tegra: gart: Fix NULL pointer dereference

Fix NULL pointer dereference on IOMMU domain destruction that happens because clients list is being iterated unsafely and its elements are getting deleted during the iteration. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding --- drivers/iommu/tegra-gart.c | 4 ++-- 1 file changed, 2

[PATCH v6 10/21] memory: tegra: Read client ID on GART page fault

With the device tree binding changes, now Memory Controller has access to GART registers. Hence it is now possible to read client ID on GART page fault to get information about what memory client causes the fault. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/mc.c | 12 ++-- 1

[PATCH v6 11/21] memory: tegra: Use of_device_get_match_data()

There is no need to match device with the DT node since it was already matched, use of_device_get_match_data() helper to get the match-data. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/mc.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git

[PATCH v6 02/21] iommu/tegra: gart: Clean up driver probe errors handling

Properly clean up allocated resources on the drivers probe failure and remove unneeded checks. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding --- drivers/iommu/tegra-gart.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/tegra-gart.c

[PATCH v6 07/21] ARM: dts: tegra20: Update Memory Controller node to the new binding

Device tree binding of Memory Controller has been changed: GART has been squashed into the MC, there are a new mandatory clock and #iommu-cells properties, the compatible has been changed to 'tegra20-mc-gart'. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 15

Re: [PATCH 12/34] powerpc/cell: move dma direct window setup out of dma_configure

Christoph Hellwig writes: > Configure the dma settings at device setup time, and stop playing games > with get_pci_dma_ops. This prepares for using the common dma_configure > code later on. > > Signed-off-by: Christoph Hellwig > --- > arch/powerpc/platforms/cell/iommu.c | 20