On Mon, 9 Dec 2019 19:05:01 +0100
Jean-Philippe Brucker wrote:
> Add support for Substream ID and PASIDs to the SMMUv3 driver.
> Changes since v2 [1]:
>
> * Split preparatory work into patches 5, 6, 8 and 9.
>
> * Added patch 1. Not strictly relevant, but since we're moving the DMA
>
On Mon, 9 Dec 2019 19:05:02 +0100
Jean-Philippe Brucker wrote:
> Since commit 518a2f1925c3 ("dma-mapping: zero memory returned from
> dma_alloc_*"), dma_alloc_* always initializes memory to zero, so there
> is no need to use dma_zalloc_* or pass the __GFP_ZERO flag anymore.
>
> The flag was
On 12/11/19 9:43 PM, Lu Baolu wrote:
The VT-d spec defines the BIOS considerations about RMRR in section 8.4:
"
BIOS must report the RMRR reported memory addresses as reserved (or as
EFI runtime) in the system memory map returned through methods such as
INT15, EFI GetMemoryMap etc.
"
So we
On Mon, 9 Dec 2019 19:05:11 +0100
Jean-Philippe Brucker wrote:
> The SMMU can support up to 20 bits of SSID. Add a second level of page
> tables to accommodate this. Devices that support more than 1024 SSIDs now
> have a table of 1024 L1 entries (8kB), pointing to tables of 1024 context
>
On Thu, 12 Dec 2019, David Rientjes wrote:
> Since all DMA must be unencrypted in this case, what happens if all
> dma_direct_alloc_pages() calls go through the DMA pool in
> kernel/dma/remap.c when force_dma_unencrypted(dev) == true since
> __PAGE_ENC is cleared for these ptes? (Ignoring for
Hi Allen,
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On Behalf
> Of Lu Baolu
> Sent: Wednesday, December 11, 2019 10:12 AM
> To: Joerg Roedel ; David Woodhouse ;
> Subject: [PATCH v3 5/6] iommu/vt-d: Flush PASID-based iotlb for iova over
> first level
>
> When software
Hi Allen,
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On Behalf
> Of Lu Baolu
> Sent: Wednesday, December 11, 2019 10:12 AM
> Subject: [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over first
> level
>
> Intel VT-d in scalable mode supports two types of page
Hi Liu Yi,
Thanks for reviewing my patch.
On 12/13/19 5:23 PM, Liu, Yi L wrote:
From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On Behalf
Of Lu Baolu
Sent: Wednesday, December 11, 2019 10:12 AM
Subject: [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over first
On 12/13/19 10:31 PM, Barret Rhoden wrote:
On 12/11/19 9:43 PM, Lu Baolu wrote:
The VT-d spec defines the BIOS considerations about RMRR in section 8.4:
"
BIOS must report the RMRR reported memory addresses as reserved (or as
EFI runtime) in the system memory map returned through methods such
Hi Jerry,
On 12/13/19 1:36 PM, Jerry Snitselaar wrote:
Currently the reserved region for ISA is allocated with no
permissions. If a dma domain is being used, mapping this region will
fail. Set the permissions to DMA_PTE_READ|DMA_PTE_WRITE.
Cc: Joerg Roedel
Cc: Lu Baolu
Cc:
Hi Liu Yi,
On 12/13/19 7:42 PM, Liu, Yi L wrote:
From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On Behalf
Of Lu Baolu
Sent: Wednesday, December 11, 2019 10:12 AM
To: Joerg Roedel ; David Woodhouse ;
Subject: [PATCH v3 5/6] iommu/vt-d: Flush PASID-based iotlb for iova over
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