Hi,
last week I spent in the hospital and had an unplanned surgery from
which I am recovering now. The recovery will take a few weeks, which
unfortunatly does not allow me to fulfill my IOMMU maintainer duties or
do any other serious work in front of a computer.
Luckily Will Deacon volunteered
Hi Yingliang,
On 2020/11/17 10:52, Yang Yingliang wrote:
If iommu_group_get() failed, it need return error code
in iommu_probe_device().
Fixes: cf193888bfbd ("iommu: Move new probe_device path...")
Reported-by: Hulk Robot
Signed-off-by: Yang Yingliang
---
drivers/iommu/iommu.c | 4 +++-
1
Hi Shameer,
On 5/13/20 5:57 PM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Auger Eric [mailto:eric.au...@redhat.com]
>> Sent: 13 May 2020 14:29
>> To: Shameerali Kolothum Thodi ;
>> Zhangfei Gao ; eric.auger@gmail.com;
>>
Hi Eric,
First, many thanks for the respin. I will go through all of
these(iommu/vfio/Qemu)
and will do a thorough verification/tests on our hardware.
> -Original Message-
> From: Auger Eric [mailto:eric.au...@redhat.com]
> Sent: 17 November 2020 08:40
> To: Shameerali Kolothum Thodi ;
This series contains a patch to solve the longterm IOVA issue which
leizhen originally tried to address at [0].
A sieved kernel log is at the following, showing periodic dumps of IOVA
sizes, per CPU and per depot bin, per IOVA size granule:
Add a helper function to free the CPU rcache for all online CPUs.
There also exists a function of the same name in
drivers/iommu/intel/iommu.c, but the parameters are different, and there
should be no conflict.
Signed-off-by: John Garry
---
drivers/iommu/iova.c | 13 +
1 file
From: Cong Wang
Both find_iova() and __free_iova() take iova_rbtree_lock,
there is no reason to take and release it twice inside
free_iova().
Fold them into one critical section by calling the unlock
versions instead.
Signed-off-by: Cong Wang
Reviewed-by: Robin Murphy
Signed-off-by: John
Hi Shameer,
On 11/17/20 12:39 PM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger [mailto:eric.au...@redhat.com]
>> Sent: 16 November 2020 10:43
>> To: eric.auger@gmail.com; eric.au...@redhat.com;
>> iommu@lists.linux-foundation.org;
On Mon, Nov 16, 2020 at 11:48:39AM -0800, John Stultz wrote:
> On Mon, Nov 16, 2020 at 8:36 AM Will Deacon wrote:
> > On Mon, Nov 16, 2020 at 04:59:36PM +0100, Thierry Reding wrote:
> > > On Fri, Nov 06, 2020 at 04:27:10AM +, John Stultz wrote:
> > > Unfortunately, the ARM SMMU module will
Add a quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to override
the attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 10 --
include/linux/io-pgtable.h | 4
2 files changed, 12 insertions(+),
From: Sharat Masetty
The last level system cache can be partitioned to 32 different
slices of which GPU has two slices preallocated. One slice is
used for caching GPU buffers and the other slice is used for
caching the GPU SMMU pagetables. This talks to the core system
cache driver to acquire
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 9 +
From: Jordan Crouse
GPU targets with an MMU-500 attached have a slightly different process for
enabling system cache. Use the compatible string on the IOMMU phandle
to see if an MMU-500 is attached and modify the programming sequence
accordingly.
Signed-off-by: Jordan Crouse
Signed-off-by: Sai
Add iommu domain attribute for pagetable configuration which
initially will be used to set quirks like for system cache aka
last level cache to be used by client drivers like GPU to set
right attributes for caching the hardware pagetables into the
system cache and later can be extended to include
Leizhen reported some time ago that IOVA performance may degrade over time
[0], but unfortunately his solution to fix this problem was not given
attention.
To summarize, the issue is that as time goes by, the CPU rcache and depot
rcache continue to grow. As such, IOVA RB tree access time also
A similar crash to the following could be observed if initial CPU rcache
magazine allocations fail in init_iova_rcaches():
Unable to handle kernel NULL pointer dereference at virtual address
Mem abort info:
ESR = 0x9604
EC = 0x25: DABT (current EL), IL = 32 bits
SET
On 2020/11/17 17:40, Lu Baolu wrote:
Hi Yingliang,
On 2020/11/17 10:52, Yang Yingliang wrote:
If iommu_group_get() failed, it need return error code
in iommu_probe_device().
Fixes: cf193888bfbd ("iommu: Move new probe_device path...")
Reported-by: Hulk Robot
Signed-off-by: Yang Yingliang
Now that we have a struct domain_attr_io_pgtbl_cfg with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 7 ++-
Some hardware variants contain a system cache or the last level
cache(llc). This cache is typically a large block which is shared
by multiple clients on the SOC. GPU uses the system cache to cache
both the GPU data buffers(like textures) as well the SMMU pagetables.
This helps with improved render
From: Sharat Masetty
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
Signed-off-by: Sai
Hi Eric,
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: 16 November 2020 10:43
> To: eric.auger@gmail.com; eric.au...@redhat.com;
> iommu@lists.linux-foundation.org; linux-ker...@vger.kernel.org;
> k...@vger.kernel.org; kvm...@lists.cs.columbia.edu;
Hi Alex,
On 2020/11/17 3:56, Alex Williamson wrote:
On Thu, 12 Nov 2020 10:24:07 +0800
Lu Baolu wrote:
Add API for getting the ioasid of a subdevice (vfio/mdev). This calls
into the backend IOMMU module to get the actual value or error number
if ioasid for subdevice is not supported. The
Hello Konrad,
On Tue, Nov 17, 2020 at 12:00:03PM -0500, Konrad Rzeszutek Wilk wrote:
> .snip..
> > > > > Lets break this down:
> > > > >
> > > > > How does the performance improve for one single device if you
> > > > > increase the SWIOTLB?
> > > > > Is there a specific device/driver that you
Fixes: 551199aca1c3 ("lib/dma-virt: Add dma_virt_ops")
Note that the drivers had open coded versions of this earlier. I think
this goes back to the addition of the qib driver which is now gone
or the addition of the hfi1 or rxe drivers for something that still
matters
Christoph,Jason
I
On Fri, Nov 13, 2020 at 04:19:25PM -0500, Konrad Rzeszutek Wilk wrote:
> On Thu, Nov 05, 2020 at 09:20:45PM +, Ashish Kalra wrote:
> > On Thu, Nov 05, 2020 at 03:20:07PM -0500, Konrad Rzeszutek Wilk wrote:
> > > On Thu, Nov 05, 2020 at 07:38:28PM +, Ashish Kalra wrote:
> > > > On Thu, Nov
On 11/13/20 1:36 AM, santosh.shilim...@oracle.com wrote:
+ Ka-Cheong
On 11/12/20 5:23 AM, Jason Gunthorpe wrote:
On Thu, Nov 12, 2020 at 10:40:30AM +0100, Christoph Hellwig wrote:
ping?
On Fri, Nov 06, 2020 at 07:19:31PM +0100, Christoph Hellwig wrote:
Hi Jason,
this series switches the
.snip..
> > > > Lets break this down:
> > > >
> > > > How does the performance improve for one single device if you increase
> > > > the SWIOTLB?
> > > > Is there a specific device/driver that you can talk about that improve
> > > > with this patch?
> > > >
> > > >
> > >
> > > Yes, these are
Hello Konrad,
Actually I didn’t get that, do you mean you are taking 1G and <=4G cases out of
the patch and only going to apply the >4G case as part of the patch ?
Thanks,
Ashish
> On Nov 17, 2020, at 11:38 AM, Kalra, Ashish wrote:
>
> Hello Konrad,
>
>> On Tue, Nov 17, 2020 at
On 11/17/20 2:50 AM, Ka-Cheong Poon wrote:
On 11/13/20 1:36 AM, santosh.shilim...@oracle.com wrote:
+ Ka-Cheong
On 11/12/20 5:23 AM, Jason Gunthorpe wrote:
On Thu, Nov 12, 2020 at 10:40:30AM +0100, Christoph Hellwig wrote:
ping?
On Fri, Nov 06, 2020 at 07:19:31PM +0100, Christoph Hellwig
From: Ashish Kalra
For SEV, all DMA to and from guest has to use shared
(un-encrypted) pages. SEV uses SWIOTLB to make this
happen without requiring changes to device drivers.
However, depending on workload being run, the default
64MB of SWIOTLB might not be enough and SWIOTLB
may run out of
On Fri, Nov 06, 2020 at 07:19:31PM +0100, Christoph Hellwig wrote:
> Hi Jason,
>
> this series switches the RDMA core to opencode the special case of
> devices bypassing the DMA mapping in the RDMA ULPs. The virt ops
> have caused a bit of trouble due to the P2P code node working with
> them due
On Tue, Nov 17, 2020 at 07:04:59PM +, Kalra, Ashish wrote:
> Hello Konrad,
>
> Actually I didn’t get that, do you mean you are taking 1G and <=4G cases out
> of the patch and only going to apply the >4G case as part of the patch ?
That was the thought, but now I am wondering how TDX is
On Wed, 30 Sep 2020 13:14:23 +0530, vji...@codeaurora.org wrote:
> When ever a new iova alloc request comes iova is always searched
> from the cached node and the nodes which are previous to cached
> node. So, even if there is free iova space available in the nodes
> which are next to the cached
On Fri, 23 Oct 2020 06:48:27 +, Chen Jun wrote:
> iommu_sva_unbind_device has no return value.
>
> Remove the description of the return value of the function.
Applied to arm64 (for-next/iommu/misc), thanks!
[1/1] iommu: Modify the description of iommu_sva_unbind_device
On Sun, 15 Nov 2020 21:59:51 +0100, Lukas Bulwahn wrote:
> Commit 6ee1b77ba3ac ("iommu/vt-d: Add svm/sva invalidate function")
> introduced intel_iommu_sva_invalidate() when CONFIG_INTEL_IOMMU_SVM.
> This function uses the dedicated static variable inv_type_granu_table
> and functions
On Tue, Nov 10, 2020 at 01:56:57PM +, Will Deacon wrote:
> Please can you pull these Arm SMMU updates for 5.11 so that they can get
> into -next? I think Bjorn is keen to get a bunch of DT updates moving, so
> the sooner we can get this lot out there, the better. Summary in the tag.
>
> There
Hey Suravee (it's been a while!),
On Fri, Nov 13, 2020 at 12:57:18PM +0700, Suravee Suthikulpanit wrote:
> Please ignore to include the V3. I am working on V4 to resubmit.
Please can you put me on CC for that?
Thanks,
Will
___
iommu mailing list
On Wed, Oct 28, 2020 at 11:18:24PM +, Suravee Suthikulpanit wrote:
> AMD IOMMU requires 4k-aligned pages for the event log, the PPR log,
> and the completion wait write-back regions. However, when allocating
> the pages, they could be part of large mapping (e.g. 2M) page.
> This causes #PF due
+Will
Please consider this patch for v5.10.
Best regards,
baolu
On 2020/11/10 15:19, Zhenzhong Duan wrote:
"intel_iommu=off" command line is used to disable iommu but iommu is force
enabled in a tboot system for security reason.
However for better performance on high speed network device, a
Hi Christoph
I have been testing with real hardware on arm64 your patchset. And uvc
performs 20 times better using Kieran's test
https://github.com/ribalda/linux/tree/uvc-noncontiguous
These are the result of running yavta --capture=1000
dma_alloc_noncontiguous
frames: 999
packets: 999
On Tue, Nov 17, 2020 at 11:09:53AM +0100, Joerg Roedel wrote:
> Luckily Will Deacon volunteered to handle incoming IOMMU patches and
> send them upstream. So please Cc him on any patches that you want to
> have merged upstream for the next release and on important fixes for
> v5.10. The patches
On Tue, Nov 17, 2020 at 07:11:28PM +0800, Yang Yingliang wrote:
> On 2020/11/17 17:40, Lu Baolu wrote:
> > On 2020/11/17 10:52, Yang Yingliang wrote:
> > > If iommu_group_get() failed, it need return error code
> > > in iommu_probe_device().
> > >
> > > Fixes: cf193888bfbd ("iommu: Move new
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