Hi Jason,
On 2022/5/17 02:06, Jason Gunthorpe wrote:
+static __init int tboot_force_iommu(void)
+{
+ if (!tboot_enabled())
+ return 0;
+
+ if (no_iommu || dmar_disabled)
+ pr_warn("Forcing Intel-IOMMU to enabled\n");
Unrelated, but when we are in the
On Tue, May 10, 2022 at 10:14:00PM +1000, Nicholas Piggin wrote:
> Excerpts from Ricardo Neri's message of May 6, 2022 10:00 am:
> > The HPET-based hardlockup detector relies on the TSC to determine if an
> > observed NMI interrupt was originated by HPET timer. Hence, this detector
> > can no
On 2022-05-16 16:31, Chaitanya Kulkarni wrote:
> Do you have any plans to re-spin this ?
I didn't get any feedback this cycle, so there haven't been any changes.
I'll probably do a rebase and resend after the merge window.
Logan
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Hi Jonathan,
On 2022/5/16 22:17, Jonathan Cameron wrote:
On Mon, 16 May 2022 20:52:19 +0800
Yicong Yang wrote:
From: Qi Liu
Use find_pmu_for_event() to simplify logic in auxtrace_record__init().
Possibly reword as
"Add find_pmu_for_event() and use to simplify logic in
On 4/7/22 08:46, Logan Gunthorpe wrote:
> Hi,
>
> This patchset continues my work to add userspace P2PDMA access using
> O_DIRECT NVMe devices. This posting contains some minor fixes and a
> rebase onto v5.18-rc1 which contains cleanup from Christoph around
> free_zone_device_page() that helps to
Hi Jason,
On Mon, 16 May 2022 15:06:28 -0300, Jason Gunthorpe wrote:
> Unrelated, but when we are in the special secure IOMMU modes, do we
> force ATS off? Specifically does the IOMMU reject TLPs that are marked
> as translated?
Yes, VT-d context entry has a Device TLB Enable bit, if 0, it
On 2022/5/16 22:20, Jonathan Cameron wrote:
On Mon, 16 May 2022 20:52:20 +0800
Yicong Yang wrote:
From: Qi Liu
HiSilicon PCIe tune and trace device (PTT) could dynamically tune
the PCIe link's events, and trace the TLP headers).
This patch add support for PTT device in perf tool, so
Hi Jason,
On 2022/5/16 21:57, Jason Gunthorpe wrote:
On Mon, May 16, 2022 at 12:22:08PM +0100, Robin Murphy wrote:
On 2022-05-16 02:57, Lu Baolu wrote:
Each IOMMU driver must provide a blocking domain ops. If the hardware
supports detaching domain from device, setting blocking domain equals
On 2022/5/17 0:29, John Garry wrote:
On 16/05/2022 13:52, Yicong Yang wrote:
As requested before, please mention "perf tool" in the commit subject
"perf arm" is used referenced to previous commit, ok, will mention "perf
tool" in the commit subject next time.
Thanks,
Qi
From: Qi Liu
I don't really understand how 'childs' fit in here. The code also
doesn't seem to be usable without patch 2 and a caller of the
new functions added in patch 2, so it is rather impossible to review.
Also:
1) why is SEV/TDX so different from other cases that need bounce
buffering to treat it
Looks good,
Reviewed-by: Christoph Hellwig
we really should not keep dead code like this around.
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On Sat, 14 May 2022, Lu Baolu wrote:
> intel-iommu.h is not needed in drm/i915 anymore. Remove its include.
Thanks for the cleanups. Do you want to keep the patches together or
want us to pick this up via drm-intel?
If you want to keep the patches together,
Acked-by: Jani Nikula
for merging
On Mon, May 16, 2022 at 09:57:56AM +0800, Lu Baolu wrote:
> Each IOMMU driver must provide a blocking domain ops. If the hardware
> supports detaching domain from device, setting blocking domain equals
> detaching the existing domain from the deivce. Otherwise, an UNMANAGED
> domain without any
From: Mikko Perttunen
Add Host1x context stream IDs on systems that support Host1x context
isolation. Host1x and attached engines can use these stream IDs to
allow isolation between memory used by different processes.
The specified stream IDs must match those configured by the hypervisor,
if
From: Mikko Perttunen
Add schema information for specifying context stream IDs. This uses
the standard iommu-map property.
Signed-off-by: Mikko Perttunen
Reviewed-by: Robin Murphy
---
v3:
* New patch
v4:
* Remove memory-contexts subnode.
---
From: Mikko Perttunen
Add code to register context devices from device tree, allocate them
out and manage their refcounts.
Signed-off-by: Mikko Perttunen
---
v2:
* Directly set DMA mask instead of inheriting from Host1x.
* Use iommu-map instead of custom DT property.
v4:
* Use u64 instead of
From: Mikko Perttunen
***
New in v5:
Rebased
Renamed host1x_context to host1x_memory_context
Small change in DRM side client driver ops to reduce churn with some
upcoming changes
Add NVDEC support
***
***
New in v4:
Addressed review comments. See individual patches.
***
***
New in v3:
On 2022-05-16 11:13, Mikko Perttunen wrote:
On 5/16/22 13:07, Will Deacon wrote:
On Mon, May 16, 2022 at 11:52:54AM +0300, cyn...@kapsi.fi wrote:
From: Mikko Perttunen
Set itself as the IOMMU for the host1x context device bus, containing
"dummy" devices used for Host1x context isolation.
On 2022-05-16 02:57, Lu Baolu wrote:
Each IOMMU driver must provide a blocking domain ops. If the hardware
supports detaching domain from device, setting blocking domain equals
detaching the existing domain from the deivce. Otherwise, an UNMANAGED
domain without any mapping will be used instead.
From: Mikko Perttunen
Set itself as the IOMMU for the host1x context device bus, containing
"dummy" devices used for Host1x context isolation.
Signed-off-by: Mikko Perttunen
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 13 +
1 file changed, 13 insertions(+)
diff --git
From: Mikko Perttunen
Implement the get_streamid_offset and can_use_memory_ctx callbacks
required for supporting context isolation. Since old firmware on VIC
cannot support context isolation without hacks that we don't want to
implement, check the firmware binary to see if context isolation
From: Mikko Perttunen
The context bus is a "dummy" bus that contains struct devices that
correspond to IOMMU contexts assigned through Host1x to processes.
Even when host1x itself is built as a module, the bus is registered
in built-in code so that the built-in ARM SMMU driver is able to
On 5/16/22 13:44, Robin Murphy wrote:
On 2022-05-16 11:13, Mikko Perttunen wrote:
On 5/16/22 13:07, Will Deacon wrote:
On Mon, May 16, 2022 at 11:52:54AM +0300, cyn...@kapsi.fi wrote:
From: Mikko Perttunen
Set itself as the IOMMU for the host1x context device bus, containing
"dummy" devices
From: Mikko Perttunen
The DMACTX field determines which context, as specified in the
TRANSCFG register, is used. While during boot it doesn't matter
which is used, later on it matters and this value is reused by
the firmware.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/falcon.c |
On 02-05-22, 15:34, Geert Uytterhoeven wrote:
> Despite the name, R-Car V3U is the first member of the R-Car Gen4
> family. Hence move its compatible value to the R-Car Gen4 section.
Applied, thanks
--
~Vinod
___
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From: Yunfei Wang
The calling to kmem_cache_alloc for level 2 pgtable allocation may run
in atomic context, and it fails sometimes when DMA32 zone runs out of
memory.
Since Mediatek IOMMU hardware support at most 35bit PA in pgtable,
so add a quirk to allow the PA of pgtables support up to
From: Yunfei Wang
Add the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT support, so that allows
page table PA up to 35bit, not only in ZONE_DMA32.
Signed-off-by: Ning Li
Signed-off-by: Yunfei Wang
---
drivers/iommu/mtk_iommu.c | 29 +
1 file changed, 25 insertions(+), 4
On Mon, May 16, 2022 at 11:52:54AM +0300, cyn...@kapsi.fi wrote:
> From: Mikko Perttunen
>
> Set itself as the IOMMU for the host1x context device bus, containing
> "dummy" devices used for Host1x context isolation.
>
> Signed-off-by: Mikko Perttunen
> ---
>
Joerg,
On 5/13/22 8:07 PM, Joerg Roedel wrote:
On Mon, May 09, 2022 at 02:48:15AM -0500, Suravee Suthikulpanit wrote:
On AMD system with SNP enabled, IOMMU hardware checks the host translation
valid (TV) and guest translation valid (GV) bits in the device
table entry (DTE) before accessing the
On 5/16/22 13:07, Will Deacon wrote:
On Mon, May 16, 2022 at 11:52:54AM +0300, cyn...@kapsi.fi wrote:
From: Mikko Perttunen
Set itself as the IOMMU for the host1x context device bus, containing
"dummy" devices used for Host1x context isolation.
Signed-off-by: Mikko Perttunen
---
HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex integrated
Endpoint(RCiEP) device, providing the capability to dynamically monitor and
tune the PCIe traffic and trace the TLP headers.
Add the driver for the device to enable the trace function. Register PMU
device of PTT trace,
From: Qi Liu
Use find_pmu_for_event() to simplify logic in auxtrace_record__init().
Signed-off-by: Qi Liu
Signed-off-by: Yicong Yang
---
tools/perf/arch/arm/util/auxtrace.c | 53 ++---
1 file changed, 34 insertions(+), 19 deletions(-)
diff --git
From: Qi Liu
Add support for using 'perf report --dump-raw-trace' to parse PTT packet.
Example usage:
Output will contain raw PTT data and its textual representation, such
as:
0 0 0x5810 [0x30]: PERF_RECORD_AUXTRACE size: 0x40 offset: 0
ref: 0xa5d50c725 idx: 0 tid: -1 cpu: 0
.
. ...
Document the introduction and usage of HiSilicon PTT device driver.
Signed-off-by: Yicong Yang
Reviewed-by: Jonathan Cameron
---
Documentation/trace/hisi-ptt.rst | 307 +++
Documentation/trace/index.rst| 1 +
2 files changed, 308 insertions(+)
create mode
The DMA operations of HiSilicon PTT device can only work properly with
identical mappings. So add a quirk for the device to force the domain
as passthrough.
Acked-by: Will Deacon
Signed-off-by: Yicong Yang
Reviewed-by: John Garry
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 21
Add maintainer for driver and documentation of HiSilicon PTT device.
Signed-off-by: Yicong Yang
Reviewed-by: Jonathan Cameron
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fd768d43e048..d30a1698251c 100644
--- a/MAINTAINERS
+++
HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex
integrated Endpoint (RCiEP) device, providing the capability
to dynamically monitor and tune the PCIe traffic (tune),
and trace the TLP headers (trace).
PTT tune is designed for monitoring and adjusting PCIe link parameters.
We
Add tune function for the HiSilicon Tune and Trace device. The interface
of tune is exposed through sysfs attributes of PTT PMU device.
Signed-off-by: Yicong Yang
Reviewed-by: Jonathan Cameron
---
drivers/hwtracing/ptt/hisi_ptt.c | 157 +++
From: Qi Liu
HiSilicon PCIe tune and trace device (PTT) could dynamically tune
the PCIe link's events, and trace the TLP headers).
This patch add support for PTT device in perf tool, so users could
use 'perf record' to get TLP headers trace data.
Signed-off-by: Qi Liu
Signed-off-by: Yicong
On 5/16/2022 3:34 PM, Christoph Hellwig wrote:
I don't really understand how 'childs' fit in here. The code also
doesn't seem to be usable without patch 2 and a caller of the
new functions added in patch 2, so it is rather impossible to review.
Hi Christoph:
OK. I will merge two patches
On Mon, 16 May 2022 20:52:20 +0800
Yicong Yang wrote:
> From: Qi Liu
>
> HiSilicon PCIe tune and trace device (PTT) could dynamically tune
> the PCIe link's events, and trace the TLP headers).
>
> This patch add support for PTT device in perf tool, so users could
> use 'perf record' to get
On Mon, May 16, 2022 at 12:27:41AM -0700, Christoph Hellwig wrote:
> On Mon, May 16, 2022 at 09:57:56AM +0800, Lu Baolu wrote:
> > Each IOMMU driver must provide a blocking domain ops. If the hardware
> > supports detaching domain from device, setting blocking domain equals
> > detaching the
Hi Robin,
On 2022/5/16 19:22, Robin Murphy wrote:
On 2022-05-16 02:57, Lu Baolu wrote:
Each IOMMU driver must provide a blocking domain ops. If the hardware
supports detaching domain from device, setting blocking domain equals
detaching the existing domain from the deivce. Otherwise, an
On Mon, 16 May 2022 20:52:17 +0800
Yicong Yang wrote:
> HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex integrated
> Endpoint(RCiEP) device, providing the capability to dynamically monitor and
> tune the PCIe traffic and trace the TLP headers.
>
> Add the driver for the device
On Mon, 16 May 2022 20:52:19 +0800
Yicong Yang wrote:
> From: Qi Liu
>
> Use find_pmu_for_event() to simplify logic in auxtrace_record__init().
Possibly reword as
"Add find_pmu_for_event() and use to simplify logic in
auxtrace_record_init(). find_pmu_for_event() will be
reused in subsequent
On Mon, May 16, 2022 at 12:22:08PM +0100, Robin Murphy wrote:
> On 2022-05-16 02:57, Lu Baolu wrote:
> > Each IOMMU driver must provide a blocking domain ops. If the hardware
> > supports detaching domain from device, setting blocking domain equals
> > detaching the existing domain from the
For streaming DMA mappings involving an IOMMU and whose IOVA len regularly
exceeds the IOVA rcache upper limit (meaning that they are not cached),
performance can be reduced.
Add the IOMMU callback for DMA mapping API dma_max_mapping_size(), which
allows the drivers to know the mapping limit and
On Fri, May 13, 2022 at 12:26 PM Saravana Kannan wrote:
>
> On Fri, May 13, 2022 at 6:58 AM Rob Herring wrote:
> >
> > On Fri, Apr 29, 2022 at 5:09 PM Saravana Kannan
> > wrote:
> > >
> > > The deferred probe timer that's used for this currently starts at
> > > late_initcall and runs for
On Mon, May 16, 2022 at 02:20:18PM +0300, Mikko Perttunen wrote:
> On 5/16/22 13:44, Robin Murphy wrote:
> > On 2022-05-16 11:13, Mikko Perttunen wrote:
> > > On 5/16/22 13:07, Will Deacon wrote:
> > > > On Mon, May 16, 2022 at 11:52:54AM +0300, cyn...@kapsi.fi wrote:
> > > > > From: Mikko
From: Yunfei Wang
The calling to kmem_cache_alloc for level 2 pgtable allocation may run
in atomic context, and it fails sometimes when DMA32 zone runs out of
memory.
Since Mediatek IOMMU hardware support at most 35bit PA in pgtable,
so add a quirk to allow the PA of pgtables support up to
From: Yunfei Wang
Add the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT support, so that allows
page table PA up to 35bit, not only in ZONE_DMA32.
Signed-off-by: Ning Li
Signed-off-by: Yunfei Wang
---
drivers/iommu/mtk_iommu.c | 29 +
1 file changed, 25 insertions(+), 4
On Mon, 16 May 2022 20:52:21 +0800
Yicong Yang wrote:
> From: Qi Liu
>
> Add support for using 'perf report --dump-raw-trace' to parse PTT packet.
>
> Example usage:
>
> Output will contain raw PTT data and its textual representation, such
> as:
>
> 0 0 0x5810 [0x30]: PERF_RECORD_AUXTRACE
From: Mikko Perttunen
For engines that support context isolation, allocate a context when
opening a channel, and set up stream ID offset and context fields
when submitting a job.
As of this commit, the stream ID offset and fallback stream ID
are not used when context isolation is disabled.
From: Mikko Perttunen
Add code to do stream ID switching at the beginning of a job. The
stream ID is switched to the stream ID specified by the context
passed in the job structure.
Before switching the stream ID, an OP_DONE wait is done on the
channel's engine to ensure that there is no
On Sat, May 14, 2022 at 09:43:16AM +0800, Lu Baolu wrote:
> This header file is private to the Intel IOMMU driver. Move it to the
> driver folder.
>
> Signed-off-by: Lu Baolu
> ---
> .../trace/events/intel_iommu.h => drivers/iommu/intel/trace.h | 4
> drivers/iommu/intel/dmar.c
On Sat, May 14, 2022 at 09:43:17AM +0800, Lu Baolu wrote:
> The IOMMU subsystem has already provided an interface to query whether
> the IOMMU hardware is enabled for a specific device. This changes the
> check from Intel specific intel_iommu_gfx_mapped (globally exported by
> the Intel IOMMU
On Sat, May 14, 2022 at 09:43:20AM +0800, Lu Baolu wrote:
> intel-iommu.h is not needed in kvm/x86 anymore. Remove its include.
>
> Signed-off-by: Lu Baolu
> ---
> arch/x86/kvm/x86.c | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Jason Gunthorpe
Jason
On Sat, May 14, 2022 at 09:43:18AM +0800, Lu Baolu wrote:
> The exported symbol intel_iommu_gfx_mapped is not used anywhere in the
> tree. Remove it to avoid dead code.
>
> Signed-off-by: Lu Baolu
> ---
> include/linux/intel-iommu.h | 1 -
> drivers/iommu/intel/iommu.c | 6 --
> 2 files
On Sat, May 14, 2022 at 09:43:19AM +0800, Lu Baolu wrote:
> intel-iommu.h is not needed in drm/i915 anymore. Remove its include.
>
> Signed-off-by: Lu Baolu
> ---
> drivers/gpu/drm/i915/i915_drv.h| 1 -
> drivers/gpu/drm/i915/display/intel_display.c | 1 -
>
On Sat, May 14, 2022 at 09:43:21AM +0800, Lu Baolu wrote:
> tboot_force_iommu() is only called by the Intel IOMMU driver. Move the
> helper into that driver. No functional change intended.
>
> Signed-off-by: Lu Baolu
> ---
> include/linux/tboot.h | 2 --
> arch/x86/kernel/tboot.c |
On Sat, May 14, 2022 at 09:43:22AM +0800, Lu Baolu wrote:
> This header file is private to the Intel IOMMU driver. Move it to the
> driver folder.
>
> Signed-off-by: Lu Baolu
> ---
> include/linux/intel-iommu.h => drivers/iommu/intel/iommu.h | 0
> drivers/iommu/intel/trace.h
On 5/12/22 22:00, Thierry Reding wrote:
> -277,7 +278,9 @@ static struct iommu_domain *tegra_smmu_domain_alloc(unsigned
> type)
> {
> struct tegra_smmu_as *as;
>
> - if (type != IOMMU_DOMAIN_UNMANAGED)
> + if (type != IOMMU_DOMAIN_UNMANAGED &&
> + type != IOMMU_DOMAIN_DMA
On 16/05/2022 13:52, Yicong Yang wrote:
Add tune function for the HiSilicon Tune and Trace device. The interface
of tune is exposed through sysfs attributes of PTT PMU device.
Signed-off-by: Yicong Yang
Reviewed-by: Jonathan Cameron
Apart from a comment on preferential style:
Reviewed-by:
On Fri, 13 May 2022 17:14:10 +0200, AngeloGioacchino Del Regno wrote:
> Add bindings for the MediaTek Helio X10 (MT6795) IOMMU/M4U.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
> .../bindings/iommu/mediatek,iommu.yaml| 3 +
> include/dt-bindings/memory/mt6795-larb-port.h | 96
On 16/05/2022 13:52, Yicong Yang wrote:
HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex integrated
Endpoint(RCiEP) device, providing the capability to dynamically monitor and
tune the PCIe traffic and trace the TLP headers.
Add the driver for the device to enable the trace
On Mon, 16 May 2022 11:52:50 +0300, cyn...@kapsi.fi wrote:
> From: Mikko Perttunen
>
> Add schema information for specifying context stream IDs. This uses
> the standard iommu-map property.
>
> Signed-off-by: Mikko Perttunen
> Reviewed-by: Robin Murphy
> ---
> v3:
> * New patch
> v4:
> *
On 16/05/2022 13:52, Yicong Yang wrote:
As requested before, please mention "perf tool" in the commit subject
From: Qi Liu
Use find_pmu_for_event() to simplify logic in auxtrace_record__init().
Signed-off-by: Qi Liu
Signed-off-by: Yicong Yang
---
tools/perf/arch/arm/util/auxtrace.c | 53
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