[PATCH 1/1 V3] AMD Family15h Model10-1Fh erratum 746 Workaround

2013-01-24 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Changes in V3: * Add proper commit message * Change logic to avoid unnecessary indentaion Changes in V2: * Fix logic that check the processor model. * Clear write enable bit after apply workaround *

[PATCH V4] IOMMU, AMD Family15h Model10-1Fh erratum 746 Workaround

2013-01-24 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com The IOMMU may stop processing page translations due to a perceived lack of credits for writing upstream peripheral page service request (PPR) or event logs. If the L2B miscellaneous clock gating feature is enabled the IOMMU does not

Re: [PATCH 1/1 V2] AMD Family15h Model10-1Fh erratum 746 Workaround

2013-01-24 Thread Borislav Petkov
On Wed, Jan 23, 2013 at 12:13:28PM -0600, suravee.suthikulpa...@amd.com wrote: From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Changes from V1: * Fix logic that check the processor model. * Clear writing enable bit after apply the workaround * Change function name You need a

Re: [PATCH V4] IOMMU, AMD Family15h Model10-1Fh erratum 746 Workaround

2013-01-24 Thread Borislav Petkov
On Thu, Jan 24, 2013 at 01:17:53PM -0600, suravee.suthikulpa...@amd.com wrote: From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com The IOMMU may stop processing page translations due to a perceived lack of credits for writing upstream peripheral page service request (PPR) or event