Re: PROBLEM: do_IRQ: [number] No irq handler for vector (irq -1)

2014-01-16 Thread Neil Horman
On Wed, Jan 15, 2014 at 09:03:05PM -0700, Alex Williamson wrote: [cc +Neil] On Tue, 2014-01-14 at 12:41 -0500, Anthony DeRobertis wrote: I repeatedly get No irq handler for vector since upgrading to 3.12. I have confirmed it happens in git master as of yesterday morning

[PATCH 09/11] ARM: dts: Add nodes for SMMUs on Calxeda ECX-2000

2014-01-16 Thread Andreas Herrmann
Cc: Rob Herring robh...@kernel.org Cc: Andreas Herrmann herrmann.der.u...@googlemail.com Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com --- arch/arm/boot/dts/ecx-2000.dts| 44 +++-- arch/arm/boot/dts/ecx-common.dtsi |9 +--- 2 files

[PATCH 01/11] iommu/arm-smmu: Introduce driver option handling

2014-01-16 Thread Andreas Herrmann
Introduce handling of driver options. Options are set based on DT information when probing an SMMU device. The first option introduced is arm,smmu-isolate-devices. (It will be used in the bus notifier block.) Cc: Andreas Herrmann herrmann.der.u...@googlemail.com Signed-off-by: Andreas Herrmann

[PATCH 02/11] iommu/arm-smmu: Introduce bus notifier block

2014-01-16 Thread Andreas Herrmann
At the moment just handle BUS_NOTIFY_BIND_DRIVER to conditionally isolate all master devices for an SMMU. Depending on DT information each device is put into its own protection domain (if possible). For configuration with one or just a few masters per SMMU that is easy to achieve. In case of

[PATCH 03/11] iommu/arm-smmu: Support buggy implementation where all config accesses are secure

2014-01-16 Thread Andreas Herrmann
In such a case we have to use secure aliases of some non-secure registers. This handling is switched on by DT property calxeda,smmu-secure-config-access for an SMMU node. Cc: Andreas Herrmann herrmann.der.u...@googlemail.com Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com ---

[PATCH 08/11] of: Increase MAX_PHANDLE_ARGS

2014-01-16 Thread Andreas Herrmann
arm-smmu driver uses of_parse_phandle_with_args when parsing DT information to determine stream IDs for a master device. Thus the number of stream IDs per master device is bound by MAX_PHANDLE_ARGS. To support Calxeda ECX-2000 hardware arm-smmu driver requires a slightly higher value for

[PATCH 05/11] iommu/arm-smmu: Check for duplicate stream IDs when registering master devices

2014-01-16 Thread Andreas Herrmann
Cc: Andreas Herrmann herrmann.der.u...@googlemail.com Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com --- drivers/iommu/arm-smmu.c | 25 ++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c

[PATCH 06/11] documentation/iommu: Update description of ARM System MMU binding

2014-01-16 Thread Andreas Herrmann
This patch adds descriptions fore new properties of device tree binding for the ARM SMMU architecture. These properties control arm-smmu driver options. Cc: Rob Herring robherri...@gmail.com Cc: Grant Likely grant.lik...@linaro.org Cc: Will Deacon will.dea...@arm.com Cc: Andreas Herrmann

[PATCH 04/11] iommu/arm-smmu: Introduce automatic stream-id-masking

2014-01-16 Thread Andreas Herrmann
Try to determine a mask that can be used for all StreamIDs of a master device. This allows to use just one SMR group instead of number-of-streamids SMR groups for a master device. Changelog: * dropped #define DEBUG * removed BUG_ON(!is_power_of_2(nr)) from determine_smr_mask by passing an

[PATCH 11/11] arm: dma-mapping: Add support to extend DMA IOMMU mappings

2014-01-16 Thread Andreas Herrmann
Instead of using just one bitmap to keep track of IO virtual addresses (handed out for IOMMU use) introduce a list of iova_ranges (each having its own bitmap). This allows us to extend existing mappings when running out of iova space for a mapping. If there is not enough space in the mapping to

Re: [PATCH 09/11] ARM: dts: Add nodes for SMMUs on Calxeda ECX-2000

2014-01-16 Thread Rob Herring
On Thu, Jan 16, 2014 at 6:44 AM, Andreas Herrmann andreas.herrm...@calxeda.com wrote: Cc: Rob Herring robh...@kernel.org Cc: Andreas Herrmann herrmann.der.u...@googlemail.com Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com One minor comment, but otherwise: Acked-by: Rob Herring

Re: [PATCH 08/11] of: Increase MAX_PHANDLE_ARGS

2014-01-16 Thread Rob Herring
On Thu, Jan 16, 2014 at 6:44 AM, Andreas Herrmann andreas.herrm...@calxeda.com wrote: arm-smmu driver uses of_parse_phandle_with_args when parsing DT information to determine stream IDs for a master device. Thus the number of stream IDs per master device is bound by MAX_PHANDLE_ARGS. To

Re: [PATCH 06/11] documentation/iommu: Update description of ARM System MMU binding

2014-01-16 Thread Rob Herring
On Thu, Jan 16, 2014 at 6:44 AM, Andreas Herrmann andreas.herrm...@calxeda.com wrote: This patch adds descriptions fore new properties of device tree binding for the ARM SMMU architecture. These properties control arm-smmu driver options. Cc: Rob Herring robherri...@gmail.com Cc: Grant

Re: [PATCH v2 3/5] intel-iommu: integrate DMA CMA

2014-01-16 Thread Akinobu Mita
2014/1/16 Marek Szyprowski m.szyprow...@samsung.com: @@ -3019,17 +3019,31 @@ static void *intel_alloc_coherent(struct device *hwdev, size_t size, flags |= GFP_DMA32; } - vaddr = (void *)__get_free_pages(flags, order); - if (!vaddr) + if

Re: [PATCH v2 2/5] x86: enable DMA CMA with swiotlb

2014-01-16 Thread Akinobu Mita
2014/1/16 Konrad Rzeszutek Wilk konrad.w...@oracle.com: On Tue, Jan 14, 2014 at 11:13:47PM +0900, Akinobu Mita wrote: The DMA Contiguous Memory Allocator support on x86 is disabled when swiotlb config option is enabled. So DMA CMA is always disabled on x86_64 because swiotlb is always

Re: [PATCH v2 1/5] x86: make dma_alloc_coherent() return zeroed memory if CMA is enabled

2014-01-16 Thread Akinobu Mita
2014/1/16 Konrad Rzeszutek Wilk konrad.w...@oracle.com: On Tue, Jan 14, 2014 at 11:13:46PM +0900, Akinobu Mita wrote: Calling dma_alloc_coherent() with __GFP_ZERO must return zeroed memory. But when the contiguous memory allocator (CMA) is enabled on x86 and the memory region is allocated by