-Original Message-
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Sent: Thursday, August 06, 2015 1:15 PM
To: Yoder Stuart-B08248; Marc Zyngier; Will Deacon
Cc: devicet...@vger.kernel.org; Lorenzo Pieralisi; a...@arndb.de;
linux-ker...@vger.kernel.org;
On Wed, 2015-08-05 at 17:18 +0200, Joerg Roedel wrote:
Hi,
here is a (bigger than I expected) patch-set which cleans up
the code to attach and detach domains to iommus in the Intel
VT-d driver.
In particular, the patch-set does:
* Remove special cases around the handling of
On Wed, 2015-08-05 at 17:18 +0200, Joerg Roedel wrote:
From: Joerg Roedel jroe...@suse.de
This array is indexed by the domain-id and contains the
pointers to the domains attached to this iommu. Modern
systems support 65536 domain ids, so that this array has a
size of 512kb, per iommu.
On Thu, Aug 6, 2015 at 9:03 AM, Yinghai Lu ying...@kernel.org wrote:
On Wed, Jul 29, 2015 at 9:07 AM, Bjorn Helgaas bhelg...@google.com wrote:
Bjorn Helgaas (11):
iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth
PCI: Allocate ATS struct during enumeration
PCI:
Hi Will,
On Thu, Aug 06, 2015 at 04:23:27PM +0100, Will Deacon wrote:
We're quite keen to get this in for arm64, since we're without IOMMU DMA
ops and need to get something upstream. Do you think this is likely to
be merged for 4.3/4.4 or would we be better off doing our own
arch-private
[...]
+PCI root complex
+
+
+Optional properties
+---
+
+- msi-map: Maps a Requester ID to an MSI controller and associated
+ msi-specifier data. The property is an arbitrary number of tuples of
+ (rid-base,msi-controller,msi-base,length),
On Wed, 2015-08-05 at 17:18 +0200, Joerg Roedel wrote:
From: Joerg Roedel jroe...@suse.de
There is no reason to pass the translation type through
multiple layers. It can also be determined in the
domain_context_mapping_one function directly.
Signed-off-by: Joerg Roedel jroe...@suse.de
On Wed, 2015-08-05 at 17:18 +0200, Joerg Roedel wrote:
From: Joerg Roedel jroe...@suse.de
Instead of searching in the domain array for already
allocated domain ids, keep track of them explicitly.
Signed-off-by: Joerg Roedel jroe...@suse.de
---
drivers/iommu/intel-iommu.c | 51
On Wed, 2015-08-05 at 17:18 +0200, Joerg Roedel wrote:
From: Joerg Roedel jroe...@suse.de
This replaces the dmar_domain-iommu_bmp with a similar
reference count array. This allows us to keep track of how
many devices behind each iommu are attached to the domain.
This is necessary for
Hi Will,
On Wednesday 05 August 2015 17:24:52 Will Deacon wrote:
On Tue, Aug 04, 2015 at 09:54:27PM +0100, Laurent Pinchart wrote:
On Tuesday 04 August 2015 15:56:42 Russell King - ARM Linux wrote:
On Tue, Aug 04, 2015 at 03:47:13PM +0100, Robin Murphy wrote:
On 04/08/15 14:16, Laurent
On 05/08/15 17:51, Mark Rutland wrote:
Rob,
Do you have any objections to this, or are you happy to take this patch?
There's a user of this binding (the GICv3 ITS) queued for v4.3 already in
the tip tree, so either we either need to be ok with this binding or we
need to rework that before
Hi Joerg,
Here are the arm-smmu and io-pgtable updates I have for 4.3. Main
changes include:
* Preparation for MSI support for SMMUv3 devices (full support will
likely come in 4.4, since the IRQ core needs some work to support
non-PCI devices).
* A couple of minor fixes in the
Joerg,
On Fri, Jul 31, 2015 at 06:18:27PM +0100, Robin Murphy wrote:
Taking inspiration from the existing arch/arm code, break out some
generic functions to interface the DMA-API to the IOMMU-API. This will
do the bulk of the heavy lifting for IOMMU-backed dma-mapping.
Signed-off-by: Robin
Hi Tirumalesh,
I think this looks pretty good now, just one small comment below.
On Wed, Aug 05, 2015 at 05:54:28PM +0100, Tirumalesh Chalamarla wrote:
The SMMU architecture defines two different behaviors when 64-bit
registers are written with 32-bit writes. The first behavior causes
zero
On Wed, Jul 29, 2015 at 9:07 AM, Bjorn Helgaas bhelg...@google.com wrote:
On Mon, Jul 20, 2015 at 07:13:49PM -0500, Bjorn Helgaas wrote:
Gregor reported a deadlock [1] when enabling a VF that supports ATS.
This series is intended to fix that. The second patch should be enough to
fix the
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