Re: [RFC PATCH 30/30] vfio: Allow to bind foreign task

On Mon, 27 Feb 2017 19:54:41 + Jean-Philippe Brucker wrote: > Let the process that owns the device create an address space bond on > behalf of another process. We add a pid argument to the BIND_TASK ioctl, > allowing the caller to bind a foreign task. The

Re: [RFC PATCH 29/30] vfio: Add support for Shared Virtual Memory

On Mon, 27 Feb 2017 19:54:40 + Jean-Philippe Brucker wrote: > Add two new ioctl for VFIO devices. VFIO_DEVICE_BIND_TASK creates a bond > between a device and a process address space, identified by a > device-specific ID named PASID. This allows the device to

[RFC PATCH 02/30] iommu/arm-smmu-v3: Link groups and domains

When removing a mapping from a domain, we need to send an invalidation to all of devices that might have stored it in their Address Translation Cache (ATC). This requires a lookup from smmu_domain to smmu_group. Add a list of groups in each domain. Although this domain-group link is already

[RFC PATCH 07/30] iommu/arm-smmu-v3: Add second level of context descriptor table

The SMMU can support up to 20 bits of SSID. Add a second level of page tables to accommodate this. Devices without support for SSID still have a single context descriptor, but the others now have a first table of 1024 entries (8kB), pointing to tables of 1024 context descriptors (64kB), allocated

[RFC PATCH 12/30] iommu/arm-smmu-v3: Keep track of process address spaces

Binding to a task requires the following steps: * Pin down the mm context, and use its ASID to tag SMMU mappings. If the ASID is already in use by the SMMU for a domain using the DMA API, abort the binding. We can steal the domain's ASID since it is allocated by the SMMU, but this deserves

[RFC PATCH 08/30] iommu/arm-smmu-v3: Add support for VHE

ARMv8.1 extensions added Virtualization Host Extensions (VHE), which allow to run a host kernel at EL2. When using normal DMA, Device and CPU address spaces are orthogonal, and do not need to implement the same capabilities, so VHE hasn't been in use on the SMMU side until now. With shared

[RFC PATCH 30/30] vfio: Allow to bind foreign task

Let the process that owns the device create an address space bond on behalf of another process. We add a pid argument to the BIND_TASK ioctl, allowing the caller to bind a foreign task. The expected program flow in this case is: * Process A creates the VFIO context and initializes the device. *

[RFC PATCH 29/30] vfio: Add support for Shared Virtual Memory

Add two new ioctl for VFIO devices. VFIO_DEVICE_BIND_TASK creates a bond between a device and a process address space, identified by a device-specific ID named PASID. This allows the device to target DMA transactions at the process virtual addresses without a need for mapping and unmapping buffers

[RFC PATCH 27/30] iommu/arm-smmu-v3: Handle PRI queue overflow

When the PRI queue is full, it enters overflow condition, which is sticky and exited by the PRI thread once it has had time to free up some slots. During that time, no new entry is added to the queue. The SMMU automatically replies to PRI Page Requests (PPR) that have "last=1" with "success", to

[RFC PATCH 24/30] iommu: Specify PASID state when unbinding a task

Provide a way for device drivers to tell the IOMMU driver about the state of the PASID they are trying to decommission. When unbinding a task from a device, the IOMMU driver needs to know whether it can immediately reuse the PASID for another task, or if there is additional work to be done before

[RFC PATCH 28/30] iommu/arm-smmu-v3: Add support for Hardware Translation Table Update at stage 1

If the SMMU supports it and the kernel was built with HTTU support, enable hardware update of access and dirty flags. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 27 ++- 1 file changed, 26 insertions(+), 1

[RFC PATCH 23/30] iommu/arm-smmu-v3: Bind/unbind device and task

Now that everything is in place, implement bind and unbind operations. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 178 +++- 1 file changed, 175 insertions(+), 3 deletions(-) diff --git

[RFC PATCH 14/30] iommu/arm-smmu-v3: Share process page tables

Copy the content of TCR, MAIR and TTBR of a given task into a context descriptor. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 39 +-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git

[RFC PATCH 16/30] iommu/arm-smmu-v3: Use shared ASID set

We now have two exclusive sets of ASIDs: private and shared. SMMUv3 allows for contexts to take part in distributed TLB maintenance via the ASET bit. When this bit is 0 for a given context, TLB entries tagged with its ASID are invalidated by broadcast TLB maintenance. Set ASET=0 for task contexts.

[RFC PATCH 21/30] iommu/arm-smmu-v3: Handle device faults from PRI

When we receive a PRI Page Request (PPR) from the SMMU, it contains a context identifier SID:SSID, an IOVA and the requested access flags. Search the domain corresponding to SID:SSID, and call handle_mm_fault on its mm. If memory management is able to fix the fault, we ask the device to retry the

[RFC PATCH 20/30] iommu/arm-smmu-v3: Enable PCI PASID in masters

Enable PASID for PCI devices that support it. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 66 ++--- 1 file changed, 63 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c

[RFC PATCH 19/30] PCI: Cache PRI and PASID bits in pci_dev

Device drivers need to check if an IOMMU enabled ATS, PRI and PASID in order to know when they can use the SVM API. Cache PRI and PASID bits in the pci_dev structure, similarly to what is currently done for ATS. Signed-off-by: Jean-Philippe Brucker ---

[RFC PATCH 17/30] iommu/arm-smmu-v3: Add SVM feature checking

Aggregate all sanity-checks for SVM under a single ARM_SMMU_FEAT_SVM bit. For PCIe SVM, users also need to check FEAT_ATS and FEAT_PRI. For platform SVM, they will most likely have to check ARM_SMMU_FEAT_STALLS. Signed-off-by: Jean-Philippe Brucker ---

[RFC PATCH 09/30] iommu/arm-smmu-v3: Support broadcast TLB maintenance

The SMMUv3 can handle invalidation targeted at TLB entries with shared ASIDs. If the implementation supports broadcast TLB maintenance, enable it and keep track of it in a feature bit. The SMMU will then take into account the following CPU instruction for ASIDs in the shared set: * TLBI

[RFC PATCH 15/30] iommu/arm-smmu-v3: Steal private ASID from a domain

The SMMU only has one ASID space, so the task allocator competes with the domain allocator for ASIDs. Task ASIDs are shared with CPUs, whereas domain ASIDs are private to the SMMU, and not affected by broadcast TLB invalidations. When the task allocator pins a mm_context and gets an ASID already

[RFC PATCH 10/30] iommu/arm-smmu-v3: Add task contexts

Now that we support substreams, add the required infrastructure to use them. Each device can be attached to multiple address spaces. The default address space is the domain, and additional ones are tasks. Each task can be attached to multiple devices as well. ++

[RFC PATCH 11/30] arm64: mm: Pin down ASIDs for sharing contexts with devices

In order to enable address space sharing with the IOMMU, we introduce functions mm_context_get and mm_context_put, that pin down a context and ensure that its ASID won't be modified willy-nilly after a rollover. Pinning is necessary because, once a device is using an ASID, it needs a valid and

[RFC PATCH 04/30] iommu/arm-smmu-v3: Add support for PCI ATS

PCIe devices can implement their own TLB, named Address Translation Cache (ATC). Steps involved in the use and maintenance of such caches are: * Device sends an Address Translation Request for a given IOVA to the IOMMU. If the translation succeeds, the IOMMU returns the corresponding physical

[RFC PATCH 03/30] PCI: Move ATS declarations outside of CONFIG_PCI

Currently ATS helpers like pci_enable_ats are only defined when CONFIG_PCI is enabled. The ARM SMMU driver might get built with CONFIG_PCI disabled. It would thus have to wrap any use of ATS helpers around #ifdef CONFIG_PCI, which isn't ideal. A nicer solution is to always define these helpers.

[RFC PATCH 06/30] iommu/arm-smmu-v3: Add support for Substream IDs

At the moment, the SMMUv3 driver offers only one stage-1 or stage-2 address space to each device. SMMUv3 allows to associate multiple address spaces per device. In addition to the Stream ID (SID), that identifies a device, we can now have Substream IDs (SSID) identifying an address space. In PCIe

[RFC PATCH 05/30] iommu/arm-smmu-v3: Disable tagged pointers when ATS is in use

The ARM architecture has a "Top Byte Ignore" (TBI) option that makes the MMU mask out bits [63:56] of an address, allowing a userspace application to store data in its pointers. The ATS doesn't have an architected mechanism to enable TBI, and might create ATC entries for addresses that include a

[RFC PATCH 00/30] Add PCIe SVM support to ARM SMMUv3

Hi, This series adds support for PCI ATS, PRI and PASID extensions to the SMMUv3 driver. In systems that support it, it is now possible for some high-end devices to perform DMA into process address spaces. Page tables are shared between MMU and SMMU; page faults from devices are recoverable and

[RFC PATCH 01/30] iommu/arm-smmu-v3: Link groups and devices

Reintroduce smmu_group. This structure was removed during the generic DT bindings rework, but will be needed when implementing PCIe ATS, to lookup devices attached to a given domain. When unmapping from a domain, we need to send an invalidation to all devices that could have stored the mapping in

Re: [RFC PATCH v4 21/28] x86: Check for memory encryption on the APs

On Thu, Feb 16, 2017 at 09:46:47AM -0600, Tom Lendacky wrote: > Add support to check if memory encryption is active in the kernel and that > it has been enabled on the AP. If memory encryption is active in the kernel > but has not been enabled on the AP, then set the SYS_CFG MSR bit to enable >

Re: [RFC PATCH v4 19/28] swiotlb: Add warnings for use of bounce buffers with SME

On Thu, Feb 16, 2017 at 09:46:19AM -0600, Tom Lendacky wrote: > Add warnings to let the user know when bounce buffers are being used for > DMA when SME is active. Since the bounce buffers are not in encrypted > memory, these notifications are to allow the user to determine some > appropriate

[PATCH v1 1/2] iommu/io-pgtable-arm: Check for leaf entry before dereferencing it

From: Oleksandr Tyshchenko Do a check for already installed leaf entry at the current level before dereferencing it in order to avoid walking the page table down with wrong pointer to the next level. Signed-off-by: Oleksandr Tyshchenko

[PATCH v1 2/2] iommu/io-pgtable-arm-v7s: Check for leaf entry before dereferencing it

From: Oleksandr Tyshchenko Do a check for already installed leaf entry at the current level before dereferencing it in order to avoid walking the page table down with wrong pointer to the next level. Signed-off-by: Oleksandr Tyshchenko

[PATCH v1 0/2] Misc fixes for ARM page table allocator (long/short descriptor format)

Hi. There is a small patch series which contains the same fix for both descriptor formats based on the preceding RFC patches: https://lists.linuxfoundation.org/pipermail/iommu/2017-February/020411.html https://lists.linuxfoundation.org/pipermail/iommu/2017-February/020477.html Oleksandr