RE: [PATCH 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

> -Original Message- > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] > Sent: Tuesday, June 13, 2017 2:13 PM > To: Shameerali Kolothum Thodi > Cc: marc.zyng...@arm.com; sudeep.ho...@arm.com; will.dea...@arm.com; > robin.mur...@arm.com; hanjun@linaro.org; Gabriele Paoloni;

Re: [PATCH 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

On Tue, Jun 13, 2017 at 12:48:29PM +0100, shameer wrote: > The HiSilicon erratum 161010801 describes the limitation of HiSilicon > platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. > > On these platforms GICv3 ITS translator is presented with the deviceID > by extending the

答复: What differences and relations between SVM, HSA, HMM and Unified Memory?

That's the thing I wanna know! Thanks for your explanation. Thanks, Zongyong Wu -邮件原件- 发件人: Jerome Glisse [mailto:j.gli...@gmail.com] 发送时间: 2017年6月13日 2:44 收件人: Wuzongyong (Cordius Wu, Euler Dept) 抄送: iommu@lists.linux-foundation.org; linux-ker...@vger.kernel.org; oded.gab...@amd.com;

Re: [PATCH 01/44] firmware/ivc: use dma_mapping_error

On Thu, Jun 08, 2017 at 03:25:26PM +0200, Christoph Hellwig wrote: > DMA_ERROR_CODE is not supposed to be used by drivers. > > Signed-off-by: Christoph Hellwig > --- > drivers/firmware/tegra/ivc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Acked-by: Thierry Reding signature.

[PATCH 3/4] iommu: add qcom_iommu

An iommu driver for Qualcomm "B" family devices which do implement the ARM SMMU spec, but not in a way that is compatible with how the arm-smmu driver is designed. It seems SMMU_SCR1.GASRAE=1 so the global register space is not accessible. This means it needs to get configuration from devicetree

[PATCH 1/2] acpi:iort: Add an IORT helper function to reserve HW ITS address regions for IOMMU drivers

The helper function retrieves ITS address regions through IORT device <-> ITS mappings and reserves it so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. IOMMU drivers can use this to implement their .get_resv_regions callback. Signed-off-by: shameer

[PATCH 0/2] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI)

On certain HiSilicon platforms (Hip06/Hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI

[PATCH 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCI

Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

Hi Rafael, Lv, On Thu, Jun 08, 2017 at 07:13:24PM +0200, Rafael J. Wysocki wrote: > On Thu, Jun 8, 2017 at 6:32 PM, Lorenzo Pieralisi > wrote: > > On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote: > >> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > >> 1. Errata I

[PATCH] iommu/vt-d: constify intel_dma_ops.

File size before: textdata bss dec hex filename 32765 7581824 353478a13 drivers/iommu/intel-iommu.o File size After adding 'const': textdata bss dec hex filename 32925 5981824 353478a13 drivers/iommu/intel-iommu.o Signed-off-by

[PATCH] iommu/io-pgtable-arm-v7s: constify dummy_tlb_ops.

File size before: textdata bss dec hex filename 6146 56 962111843 drivers/iommu/io-pgtable-arm-v7s.o File size After adding 'const': textdata bss dec hex filename 6170 24 96203183b drivers/iommu/io-pgtable-arm-v7s.o