On 6/28/17 19:44, Joerg Roedel wrote:
On Mon, Jun 26, 2017 at 04:28:04AM -0500, Suravee Suthikulpanit wrote:
Pass-through devices to VM guest can get updated IRQ affinity
information via irq_set_affinity() when not running in guest mode.
Currently, AMD IOMMU driver in GA mode ignores the updat
When adding a large scatterlist entry that covers more than the L3
superpage size (1GB) but has an alignment such that we must use L2
superpages (2MB) , we give dma_pte_free_level() a range that causes it
to free the L3 pagetable we're about to populate. We fix this by telling
dma_pte_free_pagetabl
On 2017/6/28 17:32, Will Deacon wrote:
> Hi Zhen Lei,
>
> Nate (CC'd), Robin and I have been working on something very similar to
> this series, but this patch is different to what we had planned. More below.
>
> On Mon, Jun 26, 2017 at 09:38:46PM +0800, Zhen Lei wrote:
>> Because all TLBI comm
Some more data from 3DMark benchmarks:
Time Spy(DirectX 12):
- Graphics test 1:
- npt=0: 37.65 FPS
- npt=1: 24.22 FPS (36% drop)
- Graphics test 2:
- npt=0: 33.05 FPS
- npt=1: 29.65 FPS (10% drop)
- CPU test:
- npt=0: 17.35 FPS
- npt=1: 12.03 FPS (31% drop)
Fire Strike(DirectX 11):
-
On Wed, Jun 28, 2017 at 9:50 PM, Thiago Padilha wrote:
> Some more data from 3DMark benchmarks:
>
> Time Spy(DirectX 12):
> - Graphics test 1:
> - npt=0: 37.65 FPS
> - npt=1: 24.22 FPS (36% drop)
> - Graphics test 2:
> - npt=0: 33.05 FPS
> - npt=1: 29.65 FPS (10% drop)
> - CPU test:
> -
On Wed, Jun 28, 2017 at 7:34 PM, Nick Sarnie wrote:
> Hi Suravee,
>
> Thanks a lot for helping. Torcs does not appear graphically demanding
> on modern hardware, so this issue may not be easily noticeable. I was
> able to easily reproduce the problem using the Unigine Heaven
> benchmark, but I'm s
On Wed, Jun 28, 2017 at 4:33 PM, Paolo Bonzini wrote:
>
>
> On 28/06/2017 21:52, Graham Neville wrote:
>> Although not related to graphics card performance, there is definitely
>> another issue with regards to running KVM nested L2 guests when npt=1.
>>
>> Thought I'd mention this in case it helps
> -Original Message-
> From: Joerg Roedel [mailto:j...@8bytes.org]
> Sent: Wednesday, June 28, 2017 4:37 AM
> To: Jan Vesely; Deucher, Alexander
> Cc: Lendacky, Thomas; Nath, Arindam; Craig Stein; iommu@lists.linux-
> foundation.org; Duran, Leo; Suthikulpanit, Suravee
> Subject: Re: [PATCH
On 28/06/2017 21:52, Graham Neville wrote:
> Although not related to graphics card performance, there is definitely
> another issue with regards to running KVM nested L2 guests when npt=1.
>
> Thought I'd mention this in case it helps with identifying performance
> issues with NPT.
>
> I'm unab
Although not related to graphics card performance, there is definitely
another issue with regards to running KVM nested L2 guests when npt=1.
Thought I'd mention this in case it helps with identifying performance
issues with NPT.
I'm unable to start any L2 guests with KVM acceleration (--enable-k
From: Alex Williamson
Sent: June 28, 2017 3:08 PM
To: Suthikulpanit, Suravee
Cc: Steven Walter; Nick Sarnie; Paolo Bonzini;
iommu@lists.linux-foundation.org; Matthias Ehrenfeuchter; k...@vger.kernel.org;
Bridgman, John
Subject: Re: AMD Ryzen KVM/NPT/IOMMU issue
On Thu, 29 Jun 2017 01:53:5
From: Alex Williamson
Sent: June 28, 2017 3:08 PM
To: Suthikulpanit, Suravee
Cc: Steven Walter; Nick Sarnie; Paolo Bonzini;
iommu@lists.linux-foundation.org; Matthias Ehrenfeuchter; k...@vger.kernel.org;
Bridgman, John
Subject: Re: AMD Ryzen KVM/NPT/IOMMU issue
Although not related to graphics card performance, there is definitely
another issue with regards to running KVM nested L2 guests when npt=1.
Thought I'd mention this in case it helps with identifying performance
issues with NPT.
I'm unable to start any L2 guests with KVM acceleration (--enable-k
On Thu, 29 Jun 2017 01:53:57 +0700
Suravee Suthikulpanit wrote:
> On 6/29/17 00:26, Steven Walter wrote:
> >> So, I'm trying to reproduce this issue on the Ryzen system w/ the following
> >> setup:
> >>
> >> * Host kernel v4.11 (with this patch https://lkml.org/lkml/2017/6/23/295)
> >>
> >> *
On 6/29/17 00:26, Steven Walter wrote:
So, I'm trying to reproduce this issue on the Ryzen system w/ the following
setup:
* Host kernel v4.11 (with this patch https://lkml.org/lkml/2017/6/23/295)
* guest VM RHEL7.3
* guest graphic driver = radeon
* qemu-system-x86_64 --version
Q
On 15.06.17 14:46:03, Lorenzo Pieralisi wrote:
> On Thu, Jun 08, 2017 at 10:14:19AM +0530, Ganapatrao Kulkarni wrote:
> > Add code to parse proximity domain in SMMUv3 IORT table to
> > set numa node mapping for smmuv3 devices.
> >
> > Signed-off-by: Ganapatrao Kulkarni
> > ---
> > drivers/acpi/a
On Thu, 29 Jun 2017 00:23:20 +0700
Suravee Suthikulpanit wrote:
> So, I'm trying to reproduce this issue on the Ryzen system w/ the following
> setup:
>
>* Host kernel v4.11 (with this patch https://lkml.org/lkml/2017/6/23/295)
>
>* guest VM RHEL7.3
>
>* guest graphic driver = rade
On Wed, Jun 28, 2017 at 1:23 PM, Suravee Suthikulpanit
wrote:
>
>
> On 6/25/17 12:55, Nick Sarnie wrote:
>>
>> On Fri, May 5, 2017 at 1:27 PM, Alex Williamson
>> wrote:
>>>
>>> On Wed, 3 May 2017 12:28:35 -0400
>>> Nick Sarnie wrote:
>>>
On Wed, May 3, 2017 at 10:37 AM, Matthias Ehrenfeucht
On 6/25/17 12:55, Nick Sarnie wrote:
On Fri, May 5, 2017 at 1:27 PM, Alex Williamson
wrote:
On Wed, 3 May 2017 12:28:35 -0400
Nick Sarnie wrote:
On Wed, May 3, 2017 at 10:37 AM, Matthias Ehrenfeuchter wrote:
Hi,
There are a lot of messages/threads out there about bad performance while
u
On 28/06/17 17:09, Jacob Pan wrote:
> On Wed, 28 Jun 2017 12:08:23 +0200
> Joerg Roedel wrote:
>
>> On Tue, Jun 27, 2017 at 12:47:57PM -0700, Jacob Pan wrote:
>>> From: "Liu, Yi L"
>>>
>>> When a SVM capable device is assigned to a guest, the first level
>>> page tables are owned by the guest an
Hi Will/Robin,
On 6/28/17 4:46 AM, Will Deacon wrote:
> Hi Ray,
>
> Robin and I have been bashing our heads against the tlb_sync_pending flag
> this morning, and we reckon it could have something to do with your timeouts
> on MMU-500.
>
> On Tue, Jun 27, 2017 at 09:43:19AM -0700, Ray Jui wrote:
On 06/28/2017 07:00 AM, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Make sure that the device_group callback returns an ERR_PTR
> instead of NULL.
>
> Signed-off-by: Joerg Roedel
Thanks for the patch,
Acked-by: Suman Anna
regards
Suman
> ---
> drivers/iommu/omap-iommu.c | 2 +-
> 1 file c
On Wed, 28 Jun 2017 12:16:03 +0200
Joerg Roedel wrote:
> On Tue, Jun 27, 2017 at 12:47:59PM -0700, Jacob Pan wrote:
> > diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
> > index d973555..07cfd92 100644
> > --- a/drivers/iommu/iommu.c
> > +++ b/drivers/iommu/iommu.c
> > @@ -48,6 +48,7 @
On Wed, 28 Jun 2017 12:08:23 +0200
Joerg Roedel wrote:
> On Tue, Jun 27, 2017 at 12:47:57PM -0700, Jacob Pan wrote:
> > From: "Liu, Yi L"
> >
> > When a SVM capable device is assigned to a guest, the first level
> > page tables are owned by the guest and the guest PASID table
> > pointer is lin
On Wed, 28 Jun 2017 14:00:56 +0200
Joerg Roedel wrote:
> From: Joerg Roedel
>
> The generic device_group call-backs in iommu.c return NULL
> in case of error. Since they are getting ERR_PTR values from
> iommu_group_alloc(), just pass them up instead.
>
> Reported-by: Gerald Schaefer
> Signed
On 6/28/2017 4:36 AM, Joerg Roedel wrote:
Hi Tom,
Hi Joerg,
On Tue, Jun 27, 2017 at 10:12:30AM -0500, Tom Lendacky wrote:
---
drivers/iommu/amd_iommu.c | 30 --
drivers/iommu/amd_iommu_init.c | 34 --
drivers/iommu/a
On Mon, Jun 26, 2017 at 04:28:04AM -0500, Suravee Suthikulpanit wrote:
> Pass-through devices to VM guest can get updated IRQ affinity
> information via irq_set_affinity() when not running in guest mode.
> Currently, AMD IOMMU driver in GA mode ignores the updated information
> if the pass-through
On Wed, Jun 28, 2017 at 04:39:32PM +0530, Arvind Yadav wrote:
> Most dma_map_ops structures are never modified. Constify these
> structures such that these can be write-protected.
>
> Signed-off-by: Arvind Yadav
> ---
> Changes in v2:
> Added description.
>
> drivers/iommu/intel-i
From: Joerg Roedel
This callback should never return NULL. Print a warning if
that happens so that we notice and can fix it.
Signed-off-by: Joerg Roedel
---
drivers/iommu/iommu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index de09e1e.
From: Joerg Roedel
Make sure that the device_group callback returns an ERR_PTR
instead of NULL.
Signed-off-by: Joerg Roedel
---
drivers/iommu/omap-iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index 95dfca3..
From: Joerg Roedel
The generic device_group call-backs in iommu.c return NULL
in case of error. Since they are getting ERR_PTR values from
iommu_group_alloc(), just pass them up instead.
Reported-by: Gerald Schaefer
Signed-off-by: Joerg Roedel
---
drivers/iommu/iommu.c | 14 ++
1
Hi Ray,
Robin and I have been bashing our heads against the tlb_sync_pending flag
this morning, and we reckon it could have something to do with your timeouts
on MMU-500.
On Tue, Jun 27, 2017 at 09:43:19AM -0700, Ray Jui wrote:
> >> Also, in a few occasions, I observed the following message durin
Most dma_map_ops structures are never modified. Constify these
structures such that these can be write-protected.
Signed-off-by: Arvind Yadav
---
Changes in v2:
Added description.
drivers/iommu/intel-iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drive
On Wed, Jun 28, 2017 at 11:31:55AM +0200, Sebastian Andrzej Siewior wrote:
> It really does. The spin_lock() does disable preemption but this is not
> the problem. The thing is that the preempt_disable() is superfluous and
> it hurts Preempt-RT (and this is how I noticed it). Also the
> get_cpu_ptr
On Wed, Jun 28, 2017 at 03:31:16PM +0530, Arvind Yadav wrote:
> Most dma_map_ops structures are never modified. Constify these
> structures such that these can be write-protected. This file size diff
> will show the difference between data and text segment.
I know what the diff shows, but it doesn
On Tue, Jun 27, 2017 at 12:47:59PM -0700, Jacob Pan wrote:
> diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
> index d973555..07cfd92 100644
> --- a/drivers/iommu/iommu.c
> +++ b/drivers/iommu/iommu.c
> @@ -48,6 +48,7 @@ struct iommu_group {
> struct list_head devices;
> stru
On Tue, Jun 27, 2017 at 12:47:57PM -0700, Jacob Pan wrote:
> From: "Liu, Yi L"
>
> When a SVM capable device is assigned to a guest, the first level page
> tables are owned by the guest and the guest PASID table pointer is
> linked to the device context entry of the physical IOMMU.
>
> Host IOMM
Hi,
Most dma_map_ops structures are never modified. Constify these
structures such that these can be write-protected. This file size diff
will show the difference between data and text segment.
Thanks,
~arvind
On Wednesday 28 June 2017 02:23 PM, Joerg Roedel wrote:
On Tue, Jun 13, 2017 at 03:4
On Tue, Jun 27, 2017 at 12:47:56PM -0700, Jacob Pan wrote:
> Add Intel VT-d ops to the generic iommu_bind_pasid_table API
> functions.
>
> The primary use case is for direct assignment of SVM capable
> device. Originated from emulated IOMMU in the guest, the request goes
> through many layers (e.g
On Tue, Jun 27, 2017 at 12:47:55PM -0700, Jacob Pan wrote:
> +int iommu_bind_pasid_table(struct iommu_domain *domain, struct device *dev,
> + struct pasid_table_info *pasidt_binfo)
> +{
> + if (unlikely(!domain->ops->bind_pasid_table))
> + return -EINVAL;
I thin
Hi Tom,
On Tue, Jun 27, 2017 at 10:12:30AM -0500, Tom Lendacky wrote:
> ---
> drivers/iommu/amd_iommu.c | 30 --
> drivers/iommu/amd_iommu_init.c | 34 --
> drivers/iommu/amd_iommu_proto.h | 10 ++
> drivers/iommu/am
Hi Zhen Lei,
Nate (CC'd), Robin and I have been working on something very similar to
this series, but this patch is different to what we had planned. More below.
On Mon, Jun 26, 2017 at 09:38:46PM +0800, Zhen Lei wrote:
> Because all TLBI commands should be followed by a SYNC command, to make
> s
On 2017-06-28 11:22:05 [+0200], Joerg Roedel wrote:
> On Tue, Jun 27, 2017 at 06:16:47PM +0200, Sebastian Andrzej Siewior wrote:
> > Commit 583248e6620a ("iommu/iova: Disable preemption around use of
> > this_cpu_ptr()") disables preemption while accessing a per-CPU variable.
> > This does keep loc
On Tue, Jun 27, 2017 at 06:16:47PM +0200, Sebastian Andrzej Siewior wrote:
> Commit 583248e6620a ("iommu/iova: Disable preemption around use of
> this_cpu_ptr()") disables preemption while accessing a per-CPU variable.
> This does keep lockdep quiet. However I don't see the point why it is
> bad if
Hi Suravee,
On Mon, Jun 26, 2017 at 04:28:04AM -0500, Suravee Suthikulpanit wrote:
> Pass-through devices to VM guest can get updated IRQ affinity
> information via irq_set_affinity() when not running in guest mode.
> Currently, AMD IOMMU driver in GA mode ignores the updated information
> if the
On Tue, Jun 13, 2017 at 03:48:34PM +0530, Arvind Yadav wrote:
> File size before:
>text data bss dec hex filename
> 32765 7581824 353478a13 drivers/iommu/intel-iommu.o
>
> File size After adding 'const':
>text data bss dec hex
On Mon, Jun 26, 2017 at 11:42:42AM +0100, Will Deacon wrote:
> The following changes since commit 2ea659a9ef488125eb46da6eb571de5eae5c43f6:
>
> Linux 4.12-rc1 (2017-05-13 13:19:49 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/will/linux.
[Adding Alex Deucher]
Hey Alex,
On Tue, Jun 27, 2017 at 12:24:35PM -0400, Jan Vesely wrote:
> On Mon, 2017-06-26 at 14:14 +0200, Joerg Roedel wrote:
> > How does that 'dGPU goes to sleep' work? Do you put it to sleep manually
> > via sysfs or something? Or is that something that amdgpu does on i
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