Re: [PATCH v2 3/4] iommu/iova: Extend rbtree node caching

Hi Robin, I am seeing a crash when performing very basic testing on this series with a Mellanox CX4 NIC. I dug into the crash a bit, and think this patch is the culprit, but this rcache business is still mostly witchcraft to me. # ifconfig eth5 up # ifconfig eth5 down Unable to handle kernel

[PATCH 2/2] iommu/omap: Use DMA-API for performing cache flushes

The OMAP IOMMU driver was using ARM assembly code directly for flushing the MMU page table entries from the caches. This caused MMU faults on OMAP4 (Cortex-A9 based SoCs) as L2 caches were not handled due to the presence of a PL310 L2 Cache Controller. These faults were however not seen on

[PATCH 0/2] iommu/omap: Rework cache functionality with DMA Streaming API

Hi Joerg, This series adapts the OMAP IOMMU driver to use the DMA API to flush the page table/directory table entries from the CPU caches instead of the ARM assembly calls. The patches are baselined on 4.13-rc1. Following is the patch summary: 1. Patch 1 disables the OMAP IOMMU fault interrupts

Re: [PATCH] iommu/exynos: prevent building on big-endian kernels

On Fri, Jul 28, 2017 at 03:19:19PM +0200, Arnd Bergmann wrote: > Since we print the correct warning, an allmodconfig build is no longer > clean but always prints it, which defeats compile-testing: > > drivers/iommu/exynos-iommu.c:58:2: error: #warning "revisit driver if we can > enable

RE: [PATCH v4 1/2] acpi:iort: Add an IORT helper function to reserve HW ITS address regions for IOMMU drivers

> -Original Message- > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] > Sent: Friday, July 28, 2017 10:58 AM > To: Shameerali Kolothum Thodi > Cc: Robin Murphy; Guohanjun (Hanjun Guo); Gabriele Paoloni; > marc.zyng...@arm.com; John Garry; will.dea...@arm.com; Linuxarm; linux-

Re: [PATCH v3 02/12] intel-ipu3: mmu: implement driver

On Fri, Jul 28, 2017 at 11:10 PM, Robin Murphy wrote: > On 26/07/17 11:38, Tomasz Figa wrote: >> Hi Robin, >> >> On Wed, Jul 19, 2017 at 10:37 PM, Robin Murphy wrote: >>> On 19/07/17 04:12, Yong Zhi wrote: From: Tomasz Figa

Re: [PATCH v3 02/12] intel-ipu3: mmu: implement driver

On 26/07/17 11:38, Tomasz Figa wrote: > Hi Robin, > > On Wed, Jul 19, 2017 at 10:37 PM, Robin Murphy wrote: >> On 19/07/17 04:12, Yong Zhi wrote: >>> From: Tomasz Figa >>> >>> This driver translates Intel IPU3 internal virtual >>> address to physical

[PATCH] iommu/exynos: prevent building on big-endian kernels

Since we print the correct warning, an allmodconfig build is no longer clean but always prints it, which defeats compile-testing: drivers/iommu/exynos-iommu.c:58:2: error: #warning "revisit driver if we can enable big-endian ptes" [-Werror=cpp] This replaces the #warning with a dependency,

Re: [iommu:core 1/3] drivers/iommu/of_iommu.c:231:21-28: ERROR: PTR_ERR applied after initialization to constant on line 173

On Fri, 28 Jul 2017, Robin Murphy wrote: > On 28/07/17 01:26, kbuild test robot wrote: > > tree: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git core > > head: 6bd4f1c754b2fafac403073b0d8469bed1d37e2d > > commit: d87beb749281404b4b4919930b1cc6352e3746f2 [1/3] iommu/of: Handle

Re: [iommu:core 1/3] drivers/iommu/of_iommu.c:231:21-28: ERROR: PTR_ERR applied after initialization to constant on line 173

On 28/07/17 01:26, kbuild test robot wrote: > tree: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git core > head: 6bd4f1c754b2fafac403073b0d8469bed1d37e2d > commit: d87beb749281404b4b4919930b1cc6352e3746f2 [1/3] iommu/of: Handle PCI > aliases properly > > > coccinelle

Re: [PATCH v8 10/13] iommu/amd: Allocate memory below 4G for dev table if translation pre-enabled

On 07/28/17 at 01:18pm, Joerg Roedel wrote: > On Fri, Jul 28, 2017 at 07:15:53PM +0800, Baoquan He wrote: > > On 07/28/17 at 01:14pm, Joerg Roedel wrote: > > > Yes, exactly, the first device table also needs to be allocated with > > > GFP_DMA32 so that it ends up below 4GB. > > > > Got it, will

Re: [PATCH v8 10/13] iommu/amd: Allocate memory below 4G for dev table if translation pre-enabled

On Fri, Jul 28, 2017 at 07:15:53PM +0800, Baoquan He wrote: > On 07/28/17 at 01:14pm, Joerg Roedel wrote: > > Yes, exactly, the first device table also needs to be allocated with > > GFP_DMA32 so that it ends up below 4GB. > > Got it, will do. Thanks! Oh, and you also need to check in the kdump

Re: [PATCH v8 10/13] iommu/amd: Allocate memory below 4G for dev table if translation pre-enabled

On 07/28/17 at 01:14pm, Joerg Roedel wrote: > On Fri, Jul 28, 2017 at 05:06:19PM +0800, Baoquan He wrote: > > Do you mean the allocation of amd_iommu_dev_table in > > early_amd_iommu_init() also need be addressed for 1st kernel? Seems we > > don't make sure that for 1st kernel, like adding

Re: [PATCH v8 10/13] iommu/amd: Allocate memory below 4G for dev table if translation pre-enabled

On Fri, Jul 28, 2017 at 05:06:19PM +0800, Baoquan He wrote: > Do you mean the allocation of amd_iommu_dev_table in > early_amd_iommu_init() also need be addressed for 1st kernel? Seems we > don't make sure that for 1st kernel, like adding GFP_DMA32 flag when > allocate amd_iommu_dev_table in

[PATCH v2 3/3] arm: dts: mediatek: add larbid property for larb

From: Honghui Zhang Add mediatek's hardware id information for smi larb. Signed-off-by: Honghui Zhang --- arch/arm/boot/dts/mt2701.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi

[PATCH v2 2/3] dt-bindings: mediatek: add descriptions for larbid

From: Honghui Zhang This patch add larbid descritptions for mediatek's gen1 smi larb hardware. Signed-off-by: Honghui Zhang --- .../bindings/memory-controllers/mediatek,smi-larb.txt | 15 +++ 1 file changed, 15

[PATCH v2 1/3] memory: mtk-smi: add larbid handle routine

From: Honghui Zhang In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt2701"), the larb->larbid was added but not initialized. Mediatek's gen1 smi need this hardware larbid information to get the register offset which controls whether enable iommu for

Re: [PATCH 1/3] memory: mtk-smi: add larbid init routine

On Fri, 2017-07-28 at 10:59 +0100, Robin Murphy wrote: > On 28/07/17 02:15, Honghui Zhang wrote: > > On Thu, 2017-07-27 at 17:42 +0200, Matthias Brugger wrote: > >> > >> On 07/27/2017 04:01 AM, honghui.zh...@mediatek.com wrote: > >>> From: Honghui Zhang > >>> > >>> In

Re: [PATCH 1/3] memory: mtk-smi: add larbid init routine

On 28/07/17 02:15, Honghui Zhang wrote: > On Thu, 2017-07-27 at 17:42 +0200, Matthias Brugger wrote: >> >> On 07/27/2017 04:01 AM, honghui.zh...@mediatek.com wrote: >>> From: Honghui Zhang >>> >>> In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt2701"),

Re: [PATCH v4 1/2] acpi:iort: Add an IORT helper function to reserve HW ITS address regions for IOMMU drivers

On Thu, Jul 27, 2017 at 01:26:14PM +, Shameerali Kolothum Thodi wrote: > > > > -Original Message- > > From: Robin Murphy [mailto:robin.mur...@arm.com] > > Sent: Thursday, July 27, 2017 12:13 PM > > To: Shameerali Kolothum Thodi; Lorenzo Pieralisi > > Cc: Guohanjun (Hanjun Guo);

Re: [PATCH v8 13/13] iommu/amd: Disable iommu only if amd_iommu=off is specified

On 07/27/17 at 05:58pm, Joerg Roedel wrote: > On Fri, Jul 21, 2017 at 04:59:11PM +0800, Baoquan He wrote: > > From: root > > You probaly need to reset the author on this one. Oops, sorry. I made this patch on a testing machine. Will correct it. Thanks a

Re: [PATCH v8 11/13] iommu/amd: Don't copy GCR3 table root pointer

On 07/27/17 at 05:57pm, Joerg Roedel wrote: > On Fri, Jul 21, 2017 at 04:59:09PM +0800, Baoquan He wrote: > > When iommu is pre_enabled in kdump kernel, if a device is set up with > > guest translations (DTE.GV=1), then don't copy GCR3 table root pointer > > but move the device over to an empty

Re: [PATCH v8 10/13] iommu/amd: Allocate memory below 4G for dev table if translation pre-enabled

Hi Joerg, On 07/27/17 at 05:55pm, Joerg Roedel wrote: > On Fri, Jul 21, 2017 at 04:59:08PM +0800, Baoquan He wrote: > > AMD pointed out it's unsafe to update the device-table while iommu > > is enabled. It turns out that device-table pointer update is split > > up into two 32bit writes in the

Re: [PATCH v8 06/13] iommu/amd: copy old trans table from old kernel

On 07/27/17 at 05:38pm, Joerg Roedel wrote: > On Fri, Jul 21, 2017 at 04:59:04PM +0800, Baoquan He wrote: > > @@ -2128,9 +2131,43 @@ static void early_enable_iommu(struct amd_iommu > > *iommu) > > static void early_enable_iommus(void) > > { > > struct amd_iommu *iommu; > > + bool