Trying to start back up the conversation about multiple address
spaces for IOMMU devices. If you will remember Jean-Philippe posted
some patches back in February for SVM on arm-smmu-v3.
For quite some time the downstream Snapdragon kernels have supported
something we call "per-process" page tables
> -Original Message-
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Wednesday, October 04, 2017 12:22 PM
> To: Shameerali Kolothum Thodi ;
> lorenzo.pieral...@arm.com; sudeep.ho...@arm.com; will.dea...@arm.com;
> robin.mur...@arm.com; j...@8bytes.org; mark.rutl...@arm.com;
> r
On 27/09/17 14:32, Shameer Kolothum wrote:
> On some platforms msi parent address regions have to be excluded from
> normal IOVA allocation in that they are detected and decoded in a HW
> specific way by system components and so they cannot be considered normal
> IOVA address space.
>
> Add a help
Hi Robin,
On Thu, Sep 21, 2017 at 5:28 PM, Robin Murphy wrote:
> [+Christoph and Marek]
>
> On 21/09/17 09:59, Ganapatrao Kulkarni wrote:
>> Introduce smmu_alloc_coherent and smmu_free_coherent functions to
>> allocate/free dma coherent memory from NUMA node associated with SMMU.
>> Replace all
On Wed, Oct 04, 2017 at 12:22:04PM +0100, Marc Zyngier wrote:
> On 27/09/17 14:32, Shameer Kolothum wrote:
> > From: John Garry
> >
> > On some platforms msi-controller address regions have to be excluded
> > from normal IOVA allocation in that they are detected and decoded in
> > a HW specific w
Use the preferred generic node name in the example.
Signed-off-by: Geert Uytterhoeven
---
Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
b/Documenta
On 27/09/17 14:32, Shameer Kolothum wrote:
> From: John Garry
>
> On some platforms msi-controller address regions have to be excluded
> from normal IOVA allocation in that they are detected and decoded in
> a HW specific way by system components and so they cannot be considered
> normal IOVA add
On 03/10/17 23:16, David Woodhouse wrote:
> On Tue, 2017-10-03 at 19:05 +0100, Robin Murphy wrote:
>>
>> Now, there are indeed plenty of drivers and subsystems which do work on
>> lists of explicitly single pages - anything doing some variant of
>> "addr = kmap_atomic(sg_page(sg)) + sg->offset;" is
Hi Will/Lorenzo/Marc,
Any feedback on this series, please? Really appreciate if you can take a look
and let us know.
Thanks,
Shameer
> -Original Message-
> From: Shameerali Kolothum Thodi
> Sent: Wednesday, September 27, 2017 2:33 PM
> To: lorenzo.pieral...@arm.com; marc.zyng...@arm.com
On Wed, Oct 04, 2017 at 08:59:24AM +, David Laight wrote:
> Are you sure about this one?
Yes. And if you are not you haven't read either of the cover letter,
the DMA-API documentation, or the reply from Thomas to your mail
yesterday.
___
iommu maili
From: Christoph Hellwig
> Sent: 03 October 2017 11:43
>
> ia64 does not implement DMA_ATTR_NON_CONSISTENT allocations, so it doesn't
> make any sense to do any work in dma_cache_sync given that it must be a
> no-op when dma_alloc_attrs returns coherent memory.
>
> Signed-off-by: Christoph Hellwig
Le 03/10/2017 à 13:43, Christoph Hellwig a écrit :
On Tue, Oct 03, 2017 at 01:24:57PM +0200, Christophe LEROY wrote:
powerpc does not implement DMA_ATTR_NON_CONSISTENT allocations, so it
doesn't make any sense to do any work in dma_cache_sync given that it
must be a no-op when dma_alloc_attrs
12 matches
Mail list logo
