Re: [PATCH] iommu/vt-d: Fix shift overflow in qi_flush_dev_iotlb

2017-12-12 Thread Peter Xu 
On Tue, Dec 12, 2017 at 03:43:08PM -0700, Alex Williamson wrote:

[...]

> diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
> index 9a7ffd13c7f0..87888b102057 100644
> --- a/drivers/iommu/dmar.c
> +++ b/drivers/iommu/dmar.c
> @@ -1345,7 +1345,9 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 
> sid, u16 qdep,
>   struct qi_desc desc;
>  
>   if (mask) {
> - BUG_ON(addr & ((1 << (VTD_PAGE_SHIFT + mask)) - 1));
> + BUG_ON((mask > MAX_AGAW_PFN_WIDTH) ||
> +((mask == MAX_AGAW_PFN_WIDTH) && addr) ||
> +(addr & ((1 << (VTD_PAGE_SHIFT + mask)) - 1)));

Could it work if we just use 1ULL instead of 1 here?  Thanks,

-- 
Peter Xu
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Re: [PATCH v3 2/6] iommu/vt-d: Add Intel IOMMU debugfs to show context internals

2017-12-12 Thread Mehta, Sohil 
On Wed, 2017-12-13 at 10:28 +0800, Lu Baolu wrote:
> 
> > Would the recommendation be to use pr_warn instead of pr_err or
> > should
> > we entirely skip the message altogether?
> Greg ever educated me about the use of debugfs_ functions in
> this thread.
> 
> https://spinics.net/lists/linux-usb/msg159384.html
> 
> At least we should avoid the warning/error messages here.
> 

Thanks. We'll remove the error messages.
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Re: [PATCH v3 2/6] iommu/vt-d: Add Intel IOMMU debugfs to show context internals

2017-12-12 Thread Lu Baolu 
Hi,

Sorry for late reply.

On 12/08/2017 04:19 AM, Mehta, Sohil wrote:
> On Wed, 2017-12-06 at 16:16 +0800, Lu Baolu wrote:
>> Hi,
>>
>> On 12/06/2017 11:43 AM, Sohil Mehta wrote:
>>> From: Gayatri Kammela 
>>>
>>>  
>>> +   seq_printf(m, "%s Context table entries for Bus: %d\n",
>>> +  ext ? "Lower" : "", bus);
>>> +   seq_printf(m, "[entry]\tDID :B :D .F\tLow\t\tHigh\n");
>> WARNING: Prefer seq_puts to seq_printf
>> #119: FILE: drivers/iommu/intel-iommu-debug.c:59:
>> +seq_printf(m, "[entry]\tDID :B :D .F\tLow\t\tHigh\n");
>>
>> (caught by checkpatch.pl)
>>
> Hi Lu,
>
> We'll fix this and the other checkpatch.pl warnings.
>
>
>>> +
>>> +static void root_tbl_entry_show(struct seq_file *m, void *unused,
>> Why do you define the "unused" parameter which will never been used?
>> The same questions to other show functions.
>>
> Some functions in our code that are registered with seq_file needed to
> have an unused parameter since seq_file.h defines the show function as:
>   int (*show) (struct seq_file *m, void *v);
>
> But a lot of other functions including the one you pointed don't need
> to have the unused parameter. We'll remove it from those.
>
>
>>> +void __init intel_iommu_debugfs_init(void)
>>> +{
>>> +   struct dentry *iommu_debug_root;
>>> +
>>> +   iommu_debug_root = debugfs_create_dir("intel_iommu",
>>> NULL);
>>> +
>>> +   if (!iommu_debug_root) {
>>> +   pr_err("can't create debugfs dir\n");
>> I don't think we need a pr_err() here. System works well even
>> debugfs_create_dir() returns NULL.
>>
>> This is same to all pr_err() in this file.
>>
> Would the recommendation be to use pr_warn instead of pr_err or should
> we entirely skip the message altogether?

Greg ever educated me about the use of debugfs_ functions in
this thread.

https://spinics.net/lists/linux-usb/msg159384.html

At least we should avoid the warning/error messages here.

Best regards,
Lu Baolu
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Re: [PATCH] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices

2017-12-12 Thread Gary R Hook 

Please ignore. I've uncovered a problem and will re-submit.

On 12/04/2017 01:52 PM, Gary R Hook wrote:

The AMD IOMMU specification Rev 3.00 (December 2016) introduces a
new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register
offset 0030h (IOMMU Extended Feature Register).

When EPHSup=1, the IOMMU hardware requires the PPR bit of the
device table entry (DTE) to be set in order to support PPR for a
particular endpoint device.

Please see https://support.amd.com/TechDocs/48882_IOMMU.pdf for
this revision of the AMD IOMMU specification.

Signed-off-by: Gary R Hook 
---
  drivers/iommu/amd_iommu.c   |   20 +++-
  drivers/iommu/amd_iommu_types.h |2 ++
  2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index cb78933ef53f..329940ffb8c1 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -1818,7 +1818,8 @@ static bool dma_ops_domain(struct protection_domain 
*domain)
return domain->flags & PD_DMA_OPS_MASK;
  }
  
-static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)

+static void set_dte_entry(u16 devid, struct protection_domain *domain,
+ bool ats, bool ppr)
  {
u64 pte_root = 0;
u64 flags = 0;
@@ -1835,6 +1836,13 @@ static void set_dte_entry(u16 devid, struct 
protection_domain *domain, bool ats)
if (ats)
flags |= DTE_FLAG_IOTLB;
  
+	if (ppr) {

+   struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
+
+   if (iommu_feature(iommu, FEATURE_EPHSUP))
+   pte_root |= DEV_ENTRY_PPR;
+   }
+
if (domain->flags & PD_IOMMUV2_MASK) {
u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
u64 glx  = domain->glx;
@@ -1897,9 +1905,9 @@ static void do_attach(struct iommu_dev_data *dev_data,
domain->dev_cnt += 1;
  
  	/* Update device table */

-   set_dte_entry(dev_data->devid, domain, ats);
+   set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
if (alias != dev_data->devid)
-   set_dte_entry(alias, domain, ats);
+   set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
  
  	device_flush_dte(dev_data);

  }
@@ -2278,13 +2286,15 @@ static void update_device_table(struct 
protection_domain *domain)
struct iommu_dev_data *dev_data;
  
  	list_for_each_entry(dev_data, >dev_list, list) {

-   set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
+   set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
+ dev_data->iommu_v2);
  
  		if (dev_data->devid == dev_data->alias)

continue;
  
  		/* There is an alias, update device table entry for it */

-   set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);
+   set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
+ dev_data->iommu_v2);
}
  }
  
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h

index f6b24c7d8b70..6a877ebd058b 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -98,6 +98,7 @@
  #define FEATURE_HE(1ULL<<8)
  #define FEATURE_PC(1ULL<<9)
  #define FEATURE_GAM_VAPIC (1ULL<<21)
+#define FEATURE_EPHSUP (1ULL<<50)
  
  #define FEATURE_PASID_SHIFT	32

  #define FEATURE_PASID_MASK(0x1fULL << FEATURE_PASID_SHIFT)
@@ -192,6 +193,7 @@
  /* macros and definitions for device table entries */
  #define DEV_ENTRY_VALID 0x00
  #define DEV_ENTRY_TRANSLATION   0x01
+#define DEV_ENTRY_PPR   0x34
  #define DEV_ENTRY_IR0x3d
  #define DEV_ENTRY_IW0x3e
  #define DEV_ENTRY_NO_PAGE_FAULT   0x62

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[PATCH] iommu/vt-d: Fix shift overflow in qi_flush_dev_iotlb

2017-12-12 Thread Alex Williamson 
> Detected by ubsan:
>
>   UBSAN: Undefined behaviour in drivers/iommu/dmar.c:1345:3
>   shift exponent 64 is too large for 32-bit type 'int'
>   CPU: 2 PID: 1167 Comm: perf_pmu Not tainted 4.14.0-rc5+ #532
>   Hardware name: LENOVO 80MX/Lenovo E31-80, BIOS DCCN34WW(V2.03) 12/01/2015
>   Call Trace:
>
>dump_stack+0xab/0xfe
>? _atomic_dec_and_lock+0x112/0x112
>? get_unsigned_val+0x48/0x91
>ubsan_epilogue+0x9/0x49
>__ubsan_handle_shift_out_of_bounds+0x1ea/0x241
>? __ubsan_handle_load_invalid_value+0x136/0x136
>? _raw_spin_unlock_irqrestore+0x32/0x50
>? qi_submit_sync+0x642/0x820
>? qi_flush_dev_iotlb+0x158/0x1b0
>qi_flush_dev_iotlb+0x158/0x1b0
>? qi_flush_iotlb+0x110/0x110
>? do_raw_spin_lock+0x93/0x130
>iommu_flush_dev_iotlb+0xff/0x170
>iommu_flush_iova+0x168/0x220
>iova_domain_flush+0x2b/0x50
>fq_flush_timeout+0xa6/0x1e0
>? fq_ring_free+0x260/0x260
>? call_timer_fn+0xfd/0x600
>call_timer_fn+0x160/0x600
>? fq_ring_free+0x260/0x260
>? trace_timer_cancel+0x1d0/0x1d0
>? _raw_spin_unlock_irq+0x29/0x40
>? fq_ring_free+0x260/0x260
>? fq_ring_free+0x260/0x260
>run_timer_softirq+0x3bb/0x9a0
>? timer_fixup_init+0x30/0x30
>? __lock_is_held+0x35/0x150
>? sched_clock_cpu+0x14/0x180
>__do_softirq+0x159/0x9c7
>irq_exit+0x118/0x170
>smp_apic_timer_interrupt+0xda/0x530
>apic_timer_interrupt+0x9d/0xb0
>
>   RIP: 0010:__asan_load4+0xa/0x80
>   RSP: 0018:88012f647380 EFLAGS: 0246 ORIG_RAX: ff10
>   RAX: 7fff RBX: 88012f647548 RCX: 9a07ea01
>   RDX: dc00 RSI: 88012f647808 RDI: 88012f647548
>   RBP: 88012f64 R08: fbfff3b27e96 R09: fbfff3b27e95
>   R10: 9d93f4ad R11: fbfff3b27e96 R12: 88012f648000
>   R13: 88012f647558 R14: 88012f647550 R15: 88012f647808
>? stack_access_ok+0x61/0x110
>stack_access_ok+0x6d/0x110
>deref_stack_reg+0x64/0x120
>? __read_once_size_nocheck.constprop.3+0x50/0x50
>? deref_stack_reg+0x120/0x120
>? __kmalloc+0x13a/0x550
>unwind_next_frame+0xc04/0x14e0
>? kasan_kmalloc+0xa0/0xd0
>? __kmalloc+0x13a/0x550
>? __kmalloc+0x13a/0x550
>? deref_stack_reg+0x120/0x120
>? unwind_next_frame+0xf3e/0x14e0
>? i915_gem_do_execbuffer+0x4fd/0x2570 [i915]
>__save_stack_trace+0x7a/0x120
>? __kmalloc+0x13a/0x550
>save_stack+0x33/0xa0
>? save_stack+0x33/0xa0
>? kasan_kmalloc+0xa0/0xd0
>? _raw_spin_unlock+0x24/0x30
>? deactivate_slab+0x650/0xb90
>? ___slab_alloc+0x3e0/0x940
>? ___slab_alloc+0x3e0/0x940
>? i915_gem_do_execbuffer+0x4fd/0x2570 [i915]
>? __lock_is_held+0x35/0x150
>? mark_held_locks+0x33/0x130
>? kasan_unpoison_shadow+0x30/0x40
>kasan_kmalloc+0xa0/0xd0
>__kmalloc+0x13a/0x550
>? depot_save_stack+0x16a/0x7f0
>i915_gem_do_execbuffer+0x4fd/0x2570 [i915]
>? save_stack+0x92/0xa0
>? eb_relocate_slow+0x890/0x890 [i915]
>? debug_check_no_locks_freed+0x200/0x200
>? ___slab_alloc+0x3e0/0x940
>? ___slab_alloc+0x3e0/0x940
>? i915_gem_execbuffer2+0xdb/0x5f0 [i915]
>? __lock_is_held+0x35/0x150
>? i915_gem_execbuffer+0x580/0x580 [i915]
>i915_gem_execbuffer2+0x2c1/0x5f0 [i915]
>? i915_gem_execbuffer+0x580/0x580 [i915]
>? lock_downgrade+0x310/0x310
>? i915_gem_execbuffer+0x580/0x580 [i915]
>drm_ioctl_kernel+0xdc/0x190
>drm_ioctl+0x46a/0x6e0
>? i915_gem_execbuffer+0x580/0x580 [i915]
>? drm_setversion+0x430/0x430
>? lock_downgrade+0x310/0x310
>do_vfs_ioctl+0x138/0xbf0
>? ioctl_preallocate+0x180/0x180
>? do_raw_spin_unlock+0xf5/0x1d0
>? do_raw_spin_trylock+0x90/0x90
>? task_work_run+0x35/0x120
>? mark_held_locks+0x33/0x130
>? _raw_spin_unlock_irq+0x29/0x40
>? mark_held_locks+0x33/0x130
>? entry_SYSCALL_64_fastpath+0x5/0xad
>? trace_hardirqs_on_caller+0x184/0x360
>SyS_ioctl+0x3b/0x70
>entry_SYSCALL_64_fastpath+0x18/0xad
>   RIP: 0033:0x7fc0e1f0d587
>   RSP: 002b:7ffcfd9929f8 EFLAGS: 0246 ORIG_RAX: 0010
>   RAX: ffda RBX: 0006 RCX: 7fc0e1f0d587
>   RDX: 7ffcfd992a90 RSI: 40406469 RDI: 0003
>   RBP: 0003 R08: 7ffcfd992a50 R09: 
>   R10: 0073 R11: 0246 R12: 0001
>   R13:  R14:  R15: 
>
> Code is:
>
> void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
>   u64 addr, unsigned mask)
> {
>   struct qi_desc desc;
>
>   if (mask) {
>   BUG_ON(addr & ((1 << (VTD_PAGE_SHIFT + mask)) - 1));
>
> ^^^ This last line is where the warning comes. Digging deeper
> VTD_PAGE_SHIFT is 12 and the passed in mask comes from iommu_flush_iova
> (via iommu_flush_dev_iotlb) as MAX_AGAW_PFN_WIDTH which is:
>
> #define MAX_AGAW_WIDTH 64
> #define

Re: [PATCH 0/2] iommu/tegra: Add IOMMU group support

2017-12-12 Thread Alex Williamson 
On Mon, 27 Nov 2017 10:53:43 +0100
Thierry Reding  wrote:

> On Mon, Nov 27, 2017 at 10:50:53AM +0100, Thierry Reding wrote:
> > From: Thierry Reding 
> > 
> > Hi Joerg,
> > 
> > Both patches in this series are built-time dependent and therefore it
> > would be easiest if they went in via the same tree (either the IOMMU
> > tree, or the Tegra tree with your Acked-by on patch 1). Alternatively,
> > I could put patch two in a separate branch and provide a stable tag for
> > you to pull in, in order to resolve the dependency.
> > 
> > Do you have any preference?
> > 
> > Thierry
> > 
> > Thierry Reding (2):
> >   iommu/tegra: Allow devices to be grouped
> >   memory: tegra: Create SMMU display groups  
> 
> I just realized that these are actually in the wrong order. The second
> patch adds the data fields that the first patch uses. Depending on which
> merge strategy you prefer I can reorder when applying or resend in the
> correct order.


Hi Thierry,

Joerg is on paternity leave through the end of the year and I'm
handling the IOMMU tree in the interim.  Given the low traffic on
iommu/tegra-smmu.c, I'm going to suggest we take the merge path through
the Tegra tree and I'll Ack the first patch to help that along.  Please
do the necessary re-order when applying.  Thanks,

Alex

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Re: [PATCH 1/2] iommu/tegra: Allow devices to be grouped

2017-12-12 Thread Alex Williamson 
On Mon, 27 Nov 2017 10:50:54 +0100
Thierry Reding  wrote:

> From: Thierry Reding 
> 
> Implement the ->device_group() and ->of_xlate() callbacks which are used
> in order to group devices. Each group can then share a single domain.
> 
> This is implemented primarily in order to achieve the same semantics on
> Tegra210 and earlier as on Tegra186 where the Tegra SMMU was replaced by
> an ARM SMMU. Users of the IOMMU API can now use the same code to share
> domains between devices, whereas previously they used to attach each
> device individually.
> 
> Signed-off-by: Thierry Reding 
> ---
>  drivers/iommu/tegra-smmu.c | 124 
> +++--
>  1 file changed, 120 insertions(+), 4 deletions(-)


Acked-by: Alex Williamson 

> 
> diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
> index 3b6449e2cbf1..8885635d0a3b 100644
> --- a/drivers/iommu/tegra-smmu.c
> +++ b/drivers/iommu/tegra-smmu.c
> @@ -20,6 +20,12 @@
>  #include 
>  #include 
>  
> +struct tegra_smmu_group {
> + struct list_head list;
> + const struct tegra_smmu_group_soc *soc;
> + struct iommu_group *group;
> +};
> +
>  struct tegra_smmu {
>   void __iomem *regs;
>   struct device *dev;
> @@ -27,6 +33,8 @@ struct tegra_smmu {
>   struct tegra_mc *mc;
>   const struct tegra_smmu_soc *soc;
>  
> + struct list_head groups;
> +
>   unsigned long pfn_mask;
>   unsigned long tlb_mask;
>  
> @@ -703,19 +711,47 @@ static struct tegra_smmu *tegra_smmu_find(struct 
> device_node *np)
>   return mc->smmu;
>  }
>  
> +static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev,
> + struct of_phandle_args *args)
> +{
> + const struct iommu_ops *ops = smmu->iommu.ops;
> + int err;
> +
> + err = iommu_fwspec_init(dev, >of_node->fwnode, ops);
> + if (err < 0) {
> + dev_err(dev, "failed to initialize fwspec: %d\n", err);
> + return err;
> + }
> +
> + err = ops->of_xlate(dev, args);
> + if (err < 0) {
> + dev_err(dev, "failed to parse SW group ID: %d\n", err);
> + iommu_fwspec_free(dev);
> + return err;
> + }
> +
> + return 0;
> +}
> +
>  static int tegra_smmu_add_device(struct device *dev)
>  {
>   struct device_node *np = dev->of_node;
> + struct tegra_smmu *smmu = NULL;
>   struct iommu_group *group;
>   struct of_phandle_args args;
>   unsigned int index = 0;
> + int err;
>  
>   while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
> ) == 0) {
> - struct tegra_smmu *smmu;
> -
>   smmu = tegra_smmu_find(args.np);
>   if (smmu) {
> + err = tegra_smmu_configure(smmu, dev, );
> + of_node_put(args.np);
> +
> + if (err < 0)
> + return err;
> +
>   /*
>* Only a single IOMMU master interface is currently
>* supported by the Linux kernel, so abort after the
> @@ -728,9 +764,13 @@ static int tegra_smmu_add_device(struct device *dev)
>   break;
>   }
>  
> + of_node_put(args.np);
>   index++;
>   }
>  
> + if (!smmu)
> + return -ENODEV;
> +
>   group = iommu_group_get_for_dev(dev);
>   if (IS_ERR(group))
>   return PTR_ERR(group);
> @@ -751,6 +791,80 @@ static void tegra_smmu_remove_device(struct device *dev)
>   iommu_group_remove_device(dev);
>  }
>  
> +static const struct tegra_smmu_group_soc *
> +tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup)
> +{
> + unsigned int i, j;
> +
> + for (i = 0; i < smmu->soc->num_groups; i++)
> + for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++)
> + if (smmu->soc->groups[i].swgroups[j] == swgroup)
> + return >soc->groups[i];
> +
> + return NULL;
> +}
> +
> +static struct iommu_group *tegra_smmu_group_get(struct tegra_smmu *smmu,
> + unsigned int swgroup)
> +{
> + const struct tegra_smmu_group_soc *soc;
> + struct tegra_smmu_group *group;
> +
> + soc = tegra_smmu_find_group(smmu, swgroup);
> + if (!soc)
> + return NULL;
> +
> + mutex_lock(>lock);
> +
> + list_for_each_entry(group, >groups, list)
> + if (group->soc == soc) {
> + mutex_unlock(>lock);
> + return group->group;
> + }
> +
> + group = devm_kzalloc(smmu->dev, sizeof(*group), GFP_KERNEL);
> + if (!group) {
> + mutex_unlock(>lock);
> + return NULL;
> + }
> +
> + INIT_LIST_HEAD(>list);
> + group->soc = soc;
> +

RE: [PATCH v10 1/3] ACPI/IORT: Add msi address regions reservation helper

2017-12-12 Thread Shameerali Kolothum Thodi 


> -Original Message-
> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> Sent: Monday, December 11, 2017 2:45 PM
> To: Shameerali Kolothum Thodi 
> Cc: will.dea...@arm.com; robin.mur...@arm.com; marc.zyng...@arm.com;
> j...@8bytes.org; John Garry ; xuwei (O)
> ; Guohanjun (Hanjun Guo) ;
> iommu@lists.linux-foundation.org; linux-arm-ker...@lists.infradead.org; linux-
> a...@vger.kernel.org; devicet...@vger.kernel.org; Linuxarm
> 
> Subject: Re: [PATCH v10 1/3] ACPI/IORT: Add msi address regions reservation
> helper
> 
> On Wed, Nov 29, 2017 at 02:14:47PM +, Shameer Kolothum wrote:
> > On some platforms msi parent address regions have to be excluded from
> > normal IOVA allocation in that they are detected and decoded in a HW
> > specific way by system components and so they cannot be considered normal
> > IOVA address space.
> >
> > Add a helper function that retrieves ITS address regions - the msi
> > parent - through IORT device <-> ITS mappings and reserves it so that
> > these regions will not be translated by IOMMU and will be excluded from
> > IOVA allocations. The function checks for the smmu model number and
> > only applies the msi reservation if the platform requires it.
> >
> > Signed-off-by: Shameer Kolothum 
> > ---
> >  drivers/acpi/arm64/iort.c| 133
> ++-
> >  drivers/irqchip/irq-gic-v3-its.c |   3 +-
> >  include/linux/acpi_iort.h|   7 ++-
> >  3 files changed, 138 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> > index 95255ec..1c5fc36 100644
> > --- a/drivers/acpi/arm64/iort.c
> > +++ b/drivers/acpi/arm64/iort.c
> > @@ -39,6 +39,7 @@
> >  struct iort_its_msi_chip {
> > struct list_headlist;
> > struct fwnode_handle*fw_node;
> > +   phys_addr_t base_addr;
> > u32 translation_id;
> >  };
> >
> > @@ -161,14 +162,16 @@ typedef acpi_status (*iort_find_node_callback)
> >  static DEFINE_SPINLOCK(iort_msi_chip_lock);
> >
> >  /**
> > - * iort_register_domain_token() - register domain token and related ITS ID
> > - * to the list from where we can get it back later on.
> > + * iort_register_domain_token() - register domain token along with related
> > + * ITS ID and base address to the list from where we can get it back later 
> > on.
> >   * @trans_id: ITS ID.
> > + * @base: ITS base address.
> >   * @fw_node: Domain token.
> >   *
> >   * Returns: 0 on success, -ENOMEM if no memory when allocating list
> element
> >   */
> > -int iort_register_domain_token(int trans_id, struct fwnode_handle
> *fw_node)
> > +int iort_register_domain_token(int trans_id, phys_addr_t base,
> > +  struct fwnode_handle *fw_node)
> >  {
> > struct iort_its_msi_chip *its_msi_chip;
> >
> > @@ -178,6 +181,7 @@ int iort_register_domain_token(int trans_id, struct
> fwnode_handle *fw_node)
> >
> > its_msi_chip->fw_node = fw_node;
> > its_msi_chip->translation_id = trans_id;
> > +   its_msi_chip->base_addr = base;
> >
> > spin_lock(_msi_chip_lock);
> > list_add(_msi_chip->list, _msi_chip_list);
> > @@ -581,6 +585,24 @@ int iort_pmsi_get_dev_id(struct device *dev, u32
> *dev_id)
> > return -ENODEV;
> >  }
> >
> > +static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base)
> > +{
> > +   struct iort_its_msi_chip *its_msi_chip;
> > +   bool match = false;
> > +
> > +   spin_lock(_msi_chip_lock);
> > +   list_for_each_entry(its_msi_chip, _msi_chip_list, list) {
> > +   if (its_msi_chip->translation_id == its_id) {
> > +   *base = its_msi_chip->base_addr;
> > +   match = true;
> > +   break;
> > +   }
> > +   }
> > +   spin_unlock(_msi_chip_lock);
> > +
> > +   return match ? 0 : -ENODEV;
> 
> Nit: if you need to return an int, use it as the "match" variable,
> there is no point in using a bool.
> 
> int ret = -ENODEV;
> 
> if (its_msi_chip->translation_id == its_id) {
>   ...
>   ret = 0;
>   break;
> }
> 
> return ret;
> 
> > +}
> > +
> >  /**
> >   * iort_dev_find_its_id() - Find the ITS identifier for a device
> >   * @dev: The device.
> > @@ -740,6 +762,38 @@ static int __maybe_unused __get_pci_rid(struct
> pci_dev *pdev, u16 alias,
> > return 0;
> >  }
> >
> > +static bool __maybe_unused iort_hw_msi_resv_enable(struct device *dev,
> > +   struct acpi_iort_node *node)
> > +{
> > +   struct iort_fwnode *curr;
> > +   struct acpi_iort_node *iommu = NULL;
> > +   struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> > +
> > +   if (WARN_ON(!fwspec || !fwspec->iommu_fwnode))
> 
> Remove WARN_ON() here, it seems excessive.
> 
> > +   return false;
> > +
> > +   spin_lock(_fwnode_lock);
> > +