Re: [PATCH 1/2] mm: Add kernel MMU notifier to manage IOTLB/DEVTLB

Hi, Dave, Dave Hansen writes: > On 12/13/2017 07:38 PM, Lu Baolu wrote: >> 2. When vmalloc/vfree interfaces are called, the page mappings >> for kernel memory might get changed. And current code calls >> flush_tlb_kernel_range() to flush CPU TLBs only. The IOTLB

Re: [PATCH 1/2] mm: Add kernel MMU notifier to manage IOTLB/DEVTLB

On 12/13/2017 07:38 PM, Lu Baolu wrote: > 2. When vmalloc/vfree interfaces are called, the page mappings > for kernel memory might get changed. And current code calls > flush_tlb_kernel_range() to flush CPU TLBs only. The IOTLB or > DevTLB will be stale compared to that on the cpu for

Re: [PATCH 1/2] mm: Add kernel MMU notifier to manage IOTLB/DEVTLB

On 2017/12/14 11:38, Lu Baolu wrote: > Hi, > > On 12/14/2017 11:10 AM, Bob Liu wrote: >> On 2017/12/14 9:02, Lu Baolu wrote: From: Huang Ying Shared Virtual Memory (SVM) allows a kernel memory mapping to be shared between CPU and and a device which

Re: [PATCH 1/2] mm: Add kernel MMU notifier to manage IOTLB/DEVTLB

Hi, On 12/14/2017 11:10 AM, Bob Liu wrote: > On 2017/12/14 9:02, Lu Baolu wrote: >> > From: Huang Ying >> > >> > Shared Virtual Memory (SVM) allows a kernel memory mapping to be >> > shared between CPU and and a device which requested a supervisor >> > PASID. Both devices

Re: [PATCH 1/2] mm: Add kernel MMU notifier to manage IOTLB/DEVTLB

On 2017/12/14 9:02, Lu Baolu wrote: > From: Huang Ying > > Shared Virtual Memory (SVM) allows a kernel memory mapping to be > shared between CPU and and a device which requested a supervisor > PASID. Both devices and IOMMU units have TLBs that cache entries > from CPU's

[PATCH 2/2] iommu/vt-d: Register kernel MMU notifier to manage IOTLB/DEVTLB

From: Ashok Raj When a kernel client calls intel_svm_bind_mm() and gets a valid supervisor PASID, the memory mapping of init_mm will be shared between CPUs and device. IOMMU has to track the changes to this memory mapping, and get notified whenever a TLB flush is needed.

[PATCH 1/2] mm: Add kernel MMU notifier to manage IOTLB/DEVTLB

From: Huang Ying Shared Virtual Memory (SVM) allows a kernel memory mapping to be shared between CPU and and a device which requested a supervisor PASID. Both devices and IOMMU units have TLBs that cache entries from CPU's page tables. We need to get a chance to flush them

[PATCH 0/2] Kernel MMU notifier for IOTLB/DEVTLB management

Shared Virtual Memory (SVM) allows a kernel memory mapping to be shared between CPU and and a device which requested a supervisor PASID. Both devices and IOMMU units have TLBs that cache entries from CPU's page tables. We need to get a chance to flush them at the same time when we flush the CPU

Re: [PATCH] iommu/vt-d: Fix shift overflow in qi_flush_dev_iotlb

On 12/13/2017 11:15 AM, Alex Williamson wrote: On Wed, 13 Dec 2017 10:41:47 -0600 "Hook, Gary" wrote: On 12/13/2017 9:58 AM, Alex Williamson wrote: On Wed, 13 Dec 2017 15:13:55 +0800 Peter Xu wrote: On Tue, Dec 12, 2017 at 03:43:08PM -0700, Alex

Re: [PATCH] iommu/vt-d: Fix shift overflow in qi_flush_dev_iotlb

On Wed, 13 Dec 2017 10:41:47 -0600 "Hook, Gary" wrote: > On 12/13/2017 9:58 AM, Alex Williamson wrote: > > On Wed, 13 Dec 2017 15:13:55 +0800 > > Peter Xu wrote: > > > >> On Tue, Dec 12, 2017 at 03:43:08PM -0700, Alex Williamson wrote: > >> > >> [...] > >>

Re: [PATCH] iommu/vt-d: Fix shift overflow in qi_flush_dev_iotlb

On 12/13/2017 9:58 AM, Alex Williamson wrote: On Wed, 13 Dec 2017 15:13:55 +0800 Peter Xu wrote: On Tue, Dec 12, 2017 at 03:43:08PM -0700, Alex Williamson wrote: [...] diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c index 9a7ffd13c7f0..87888b102057 100644 ---

Re: [PATCH] iommu/vt-d: Fix shift overflow in qi_flush_dev_iotlb

On Wed, 13 Dec 2017 15:13:55 +0800 Peter Xu wrote: > On Tue, Dec 12, 2017 at 03:43:08PM -0700, Alex Williamson wrote: > > [...] > > > diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c > > index 9a7ffd13c7f0..87888b102057 100644 > > --- a/drivers/iommu/dmar.c > > +++

[PATCH v11 1/3] ACPI/IORT: Add msi address regions reservation helper

On some platforms msi parent address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add a helper function that retrieves ITS address regions - the

[PATCH v11 2/3] iommu/dma: Add HW MSI(GICv3 ITS) address regions reservation

Modified iommu_dma_get_resv_regions() to include GICv3 ITS region on ACPI based ARM platfiorms which may require HW MSI reservations. Signed-off-by: Shameer Kolothum Reviewed-by: Robin Murphy --- drivers/iommu/dma-iommu.c | 8 +++-

[PATCH v11 0/3] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI)

On certain HiSilicon platforms (hip06/hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI

[PATCH v11 3/3] arm64:dts:hisilicon Disable hisilicon smmu node on hip06/hip07

The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMUv3 mappings for MSI transactions. PCIe controller on these platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This makes it