Re: [PATCH 01/12] iommu-common: move to arch/sparc

On 04/16/2018 07:28 PM, David Miller wrote: > From: Anshuman Khandual > Date: Mon, 16 Apr 2018 14:26:07 +0530 > >> On 04/15/2018 08:29 PM, Christoph Hellwig wrote: >>> This code is only used by sparc, and all new iommu drivers should use the >>> drivers/iommu/

[PATCH 9/9] iommu/vt-d: Clean up PASID talbe management for SVM

The previous per iommu pasid table alloc/free interfaces are no longer used. Clean up the driver by removing it. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Signed-off-by: Lu Baolu

[PATCH 3/9] iommu/vt-d: Use global PASID for SVM usage

This patch switches PASID management for SVM from per iommu idr to the global idr. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Signed-off-by: Lu Baolu

[PATCH 8/9] iommu/vt-d: Use per-domain pasid table

This patch replaces current per iommu pasid table with the new added per domain pasid table. Each svm-capable PCI device will have its own pasid table. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L

[PATCH 5/9] iommu/vt-d: Per domain pasid table interfaces

This patch adds the interfaces for per domain pasid table management. Currently we allocate one pasid table for all devices under the scope of an IOMMU. It's insecure in the cases where multiple devices under one single IOMMU unit support PASID feature. With per domain pasid table, we can achieve

[PATCH 1/9] iommu/vt-d: Global PASID name space

This adds the system wide PASID name space for the PASID allocation. Currently we are using per IOMMU PASID name spaces which are not suitable for some use cases. For an example, one application (associated with a PASID) might talk to two physical devices simultaneously while the two devices could

[PATCH 2/9] iommu/vt-d: Decouple idr bond pointer from svm

As we move the PASID idr out of SVM code and make it serving as a global PASID name space, the consumer can specify a ptr to bind it with a PASID. We shouldn't assume that each PASID will be bond with a ptr of struct intel_svm anymore. This patch cleans up a idr_for_each_entry() usage in the SVM

[PATCH 4/9] iommu/vt-d: Move device_domain_info to header

This allows the per device iommu data to be accessed from other files. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Signed-off-by: Lu Baolu ---

[PATCH 7/9] iommu/vt-d: Calculate PTS value

Calculate PTS (PASID Table Size) value for the extended context entry from the real size of the PASID table for a domain. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Signed-off-by: Lu

[PATCH 6/9] iommu/vt-d: Allocate and free pasid table

This patch allocates PASID table for a domain at the time when it is being created (if any devices using this domain supports PASID feature), and free it when the domain is freed. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian

[PATCH 0/9] iommu/vt-d: Improve PASID id and table management

This patch set improves the PASID id and PASID table management for Intel IOMMU driver. PATCH 1~3 replace per IOMMU idr name space with a global one. Current per IOMMU idr doesn't work in some cases where one application (associated with a PASID) might talk to two physical devices simultaneously

Re: [PATCH v3 2/2] iommu/amd: Add basic debugfs infrastructure for AMD IOMMU

On Fri, 2018-04-06 at 08:17 -0500, Gary R Hook wrote: > > diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile > index 5eb1121d54b9..0ca250f626d9 100644 > --- a/drivers/iommu/Makefile > +++ b/drivers/iommu/Makefile > @@ -11,6 +11,7 @@ obj-$(CONFIG_IOMMU_IOVA) += iova.o >  

[PATCH v4 17/22] iommu/intel-svm: report device page request

If the source device of a page request has its PASID table pointer bound to a guest, the first level page tables are owned by the guest. In this case, we shall let guest OS to manage page fault. This patch uses the IOMMU fault reporting API to send fault events, possibly via VFIO, to the guest

[PATCH v4 22/22] iommu: use sva invalidate and device fault trace event

For performance and debugging purposes, these trace events help analyzing device faults and passdown invalidations that interact with IOMMU subsystem. E.g. IOMMU::00:0a.0 type=2 reason=0 addr=0x007ff000 pasid=1 group=1 last=0 prot=1 Signed-off-by: Jacob Pan

[PATCH v4 14/22] iommu: handle page response timeout

When IO page faults are reported outside IOMMU subsystem, the page request handler may fail for various reasons. E.g. a guest received page requests but did not have a chance to run for a long time. The irresponsive behavior could hold off limited resources on the pending device. There can be

[PATCH v4 21/22] trace/iommu: add sva trace events

Signed-off-by: Jacob Pan --- include/trace/events/iommu.h | 112 +++ 1 file changed, 112 insertions(+) diff --git a/include/trace/events/iommu.h b/include/trace/events/iommu.h index 72b4582..e64eb29 100644 ---

[PATCH v4 19/22] iommu/intel-svm: do not flush iotlb for viommu

vIOMMU passdown invalidation will be inclusive, PASID cache invalidation includes TLBs. See Intel VT-d Specification Ch 6.5.2.2 for details. Signed-off-by: Jacob Pan --- drivers/iommu/intel-svm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[PATCH v4 20/22] iommu/vt-d: add intel iommu page response function

This patch adds page response support for Intel VT-d. Generic response data is taken from the IOMMU API then parsed into VT-d specific response descriptor format. Signed-off-by: Jacob Pan --- drivers/iommu/intel-iommu.c | 47

[PATCH v4 18/22] iommu/intel-svm: replace dev ops with fault report API

With the introduction of generic IOMMU device fault reporting API, we can replace the private fault callback functions with standard function and event data. Signed-off-by: Jacob Pan --- drivers/iommu/intel-svm.c | 7 +-- include/linux/intel-svm.h | 20

[PATCH v4 16/22] iommu/vt-d: report non-recoverable faults to device

Currently, dmar fault IRQ handler does nothing more than rate limited printk, no critical hardware handling need to be done in IRQ context. For some use case such as vIOMMU, it might be useful to report non-recoverable faults outside host IOMMU subsystem. DMAR fault can come from both DMA and

[PATCH v4 12/22] iommu: introduce device fault report API

Traditionally, device specific faults are detected and handled within their own device drivers. When IOMMU is enabled, faults such as DMA related transactions are detected by IOMMU. There is no generic reporting mechanism to report faults back to the in-kernel device driver or the guest OS in case

[PATCH v4 10/22] iommu: introduce device fault data

Device faults detected by IOMMU can be reported outside IOMMU subsystem for further processing. This patch intends to provide a generic device fault data such that device drivers can be communicated with IOMMU faults without model specific knowledge. The proposed format is the result of

[PATCH v4 15/22] iommu/config: add build dependency for dmar

Intel VT-d interrupts come from both IRQ remapping and DMA remapping. In order to report non-recoverable faults back to device driver, we need to have access to IOMMU fault reporting APIs. This patch adds build depenency to DMAR code where fault IRQ handlers can selectively report faults.

[PATCH v4 04/22] iommu/vt-d: add bind_pasid_table function

Add Intel VT-d ops to the generic iommu_bind_pasid_table API functions. The primary use case is for direct assignment of SVM capable device. Originated from emulated IOMMU in the guest, the request goes through many layers (e.g. VFIO). Upon calling host IOMMU driver, caller passes guest PASID

[PATCH v4 05/22] iommu: introduce iommu invalidate API function

From: "Liu, Yi L" When an SVM capable device is assigned to a guest, the first level page tables are owned by the guest and the guest PASID table pointer is linked to the device context entry of the physical IOMMU. Host IOMMU driver has no knowledge of caching

[PATCH v4 13/22] iommu: introduce page response function

IO page faults can be handled outside IOMMU subsystem. For an example, when nested translation is turned on and guest owns the first level page tables, device page request can be forwared to the guest for handling faults. As the page response returns by the guest, IOMMU driver on the host need to

[PATCH v4 11/22] driver core: add per device iommu param

DMA faults can be detected by IOMMU at device level. Adding a pointer to struct device allows IOMMU subsystem to report relevant faults back to the device driver for further handling. For direct assigned device (or user space drivers), guest OS holds responsibility to handle and respond per device

[PATCH v4 03/22] iommu/vt-d: add a flag for pasid table bound status

Adding a flag in device domain into to track whether a guest or user PASID table is bound to a device. Signed-off-by: Jacob Pan --- include/linux/intel-iommu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/intel-iommu.h

[PATCH v4 09/22] iommu/vt-d: add svm/sva invalidate function

When Shared Virtual Address (SVA) is enabled for a guest OS via vIOMMU, we need to provide invalidation support at IOMMU API and driver level. This patch adds Intel VT-d specific function to implement iommu passdown invalidate API for shared virtual address. The use case is for supporting caching

[PATCH v4 08/22] iommu/vt-d: support flushing more translation cache types

When Shared Virtual Memory is exposed to a guest via vIOMMU, extended IOTLB invalidation may be passed down from outside IOMMU subsystems. This patch adds invalidation functions that can be used for additional translation cache types. Signed-off-by: Jacob Pan ---

[PATCH v4 01/22] iommu: introduce bind_pasid_table API function

Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use in the guest: https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html As part of the proposed architecture, when an SVM capable PCI device is assigned to a guest, nested mode is turned on. Guest owns the first level

[PATCH v4 06/22] iommu/vt-d: add definitions for PFSID

When SRIOV VF device IOTLB is invalidated, we need to provide the PF source ID such that IOMMU hardware can gauge the depth of invalidation queue which is shared among VFs. This is needed when device invalidation throttle (DIT) capability is supported. This patch adds bit definitions for checking

[PATCH v4 00/22] IOMMU and VT-d driver support for Shared Virtual Address (SVA)

Hi Joerg and All, (Rebased to 4.17-rc1. resend) Shared virtual address (SVA), a.k.a, Shared virtual memory (SVM) on Intel platforms allow address space sharing between device DMA and applications. SVA can reduce programming complexity and enhance security. To enable SVA in the guest, i.e. shared

[PATCH v4 07/22] iommu/vt-d: fix dev iotlb pfsid use

PFSID should be used in the invalidation descriptor for flushing device IOTLBs on SRIOV VFs. Signed-off-by: Jacob Pan --- drivers/iommu/dmar.c| 6 +++--- drivers/iommu/intel-iommu.c | 16 +++- include/linux/intel-iommu.h | 5 ++--- 3 files

Re: [PATCH 08/12] mmc: reduce use of block bounce buffers (fwd)

g, linux-s...@vger.kernel.org, net...@vger.kernel.org CC: linux-ker...@vger.kernel.org Hi Christoph, I love your patch! Perhaps something to improve: [auto build test WARNING on linus/master] [also build test WARNING on v4.17-rc1 next-20180416] [if your patch is applied to the wrong git tree,

[PATCH RFC] dma-direct: Try reallocation with GFP_DMA32 if possible

As the recent swiotlb bug revealed, we seem to have given up the direct DMA allocation too early and felt back to swiotlb allocation. The reason is that swiotlb allocator expected that dma_direct_alloc() would try harder to get pages even below 64bit DMA mask with GFP_DMA32, but the function

Re: [PATCH 01/12] iommu-common: move to arch/sparc

From: Anshuman Khandual Date: Mon, 16 Apr 2018 14:26:07 +0530 > On 04/15/2018 08:29 PM, Christoph Hellwig wrote: >> This code is only used by sparc, and all new iommu drivers should use the >> drivers/iommu/ framework. Also remove the unused exports. >> >>

Re: [PATCH 08/12] mmc: reduce use of block bounce buffers

On 16/04/18 09:50, Christoph Hellwig wrote: We can rely on the dma-mapping code to handle any DMA limits that is bigger than the ISA DMA mask for us (either using an iommu or swiotlb), so remove setting the block layer bounce limit for anything but bouncing for highmem pages. Signed-off-by:

Re: [PATCH 06/12] dma-mapping: move the NEED_DMA_MAP_STATE config symbol to lib/Kconfig

On 04/15/2018 08:29 PM, Christoph Hellwig wrote: > This way we have one central definition of it, and user can select it as > needed. Note that we now also always select it when CONFIG_DMA_API_DEBUG > is select, which fixes some incorrect checks in a few network drivers. > > Signed-off-by:

Re: [PATCH 05/12] scatterlist: move the NEED_SG_DMA_LENGTH config symbol to lib/Kconfig

On 04/15/2018 08:29 PM, Christoph Hellwig wrote: > This way we have one central definition of it, and user can select it as > needed. > > Signed-off-by: Christoph Hellwig Reviewed-by: Anshuman Khandual ___

Re: [PATCH 02/12] iommu-helper: unexport iommu_area_alloc

On 04/15/2018 08:29 PM, Christoph Hellwig wrote: > This function is only used by built-in code. > > Reviewed-by: Christoph Hellwig Reviewed-by: Anshuman Khandual ___ iommu mailing list

Re: [PATCH 04/12] iommu-helper: move the IOMMU_HELPER config symbol to lib/

On 04/15/2018 08:29 PM, Christoph Hellwig wrote: > This way we have one central definition of it, and user can select it as > needed. > > Signed-off-by: Christoph Hellwig Reviewed-by: Anshuman Khandual ___

Re: [PATCH 01/12] iommu-common: move to arch/sparc

On 04/15/2018 08:29 PM, Christoph Hellwig wrote: > This code is only used by sparc, and all new iommu drivers should use the > drivers/iommu/ framework. Also remove the unused exports. > > Signed-off-by: Christoph Hellwig Right, these functions are used only from SPARC

[PATCH 08/12] mmc: reduce use of block bounce buffers

We can rely on the dma-mapping code to handle any DMA limits that is bigger than the ISA DMA mask for us (either using an iommu or swiotlb), so remove setting the block layer bounce limit for anything but bouncing for highmem pages. Signed-off-by: Christoph Hellwig ---

[PATCH 12/12] PCI: remove PCI_DMA_BUS_IS_PHYS

This was used by the ide, scsi and networking code in the past to determine if they should bounce payloads. Now that the dma mapping always have to support dma to all physical memory (thanks to swiotlb for non-iommu systems) there is no need to this crude hack any more. Signed-off-by: Christoph

[PATCH 10/12] ide: remove the PCI_DMA_BUS_IS_PHYS check

We now have ways to deal with drainage in the block layer, and libata has been using it for ages. We also want to get rid of PCI_DMA_BUS_IS_PHYS now, so just reduce the PCI transfer size for ide - anyone who cares for performance on PCI controllers should have switched to libata long ago.

[PATCH 07/12] scsi: reduce use of block bounce buffers

We can rely on the dma-mapping code to handle any DMA limits that is bigger than the ISA DMA mask for us (either using an iommu or swiotlb), so remove setting the block layer bounce limit for anything but the unchecked_isa_dma case, or the bouncing for highmem pages. Signed-off-by: Christoph

[PATCH 11/12] net: remove the PCI_DMA_BUS_IS_PHYS check in illegal_highdma

These days the dma mapping routines must be able to handle any address supported by the device, be that using an iommu, or swiotlb if none is supported. With that the PCI_DMA_BUS_IS_PHYS check in illegal_highdma is not needed and can be removed. Signed-off-by: Christoph Hellwig ---

[PATCH 05/12] sata_nv: don't use block layer bounce buffers

sata_nv sets the block bounce limit to the reduce dma mask for ATAPI devices, which means that the iommu or swiotlb already take care of the bounce buffering, and the block bouncing can be removed. Signed-off-by: Christoph Hellwig --- drivers/ata/sata_nv.c | 62

[PATCH 06/12] memstick: don't call blk_queue_bounce_limit

All in-tree host drivers set up a proper dma mask and use the dma-mapping helpers. This means they will be able to deal with any address that we are throwing at them. Signed-off-by: Christoph Hellwig --- drivers/memstick/core/ms_block.c| 5 -

[PATCH 01/12] iscsi_tcp: don't set a bounce limit

The default already is to never bounce, so the call is a no-op. Signed-off-by: Christoph Hellwig --- drivers/scsi/iscsi_tcp.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index 2ba4b68fdb73..b025a0b74341 100644 ---

[PATCH 04/12] DAC960: don't use block layer bounce buffers

DAC960 just sets the block bounce limit to the dma mask, which means that the iommu or swiotlb already take care of the bounce buffering, and the block bouncing can be removed. Signed-off-by: Christoph Hellwig --- drivers/block/DAC960.c | 9 ++--- drivers/block/DAC960.h | 1 -

[PATCH 03/12] mtip32xx: don't use block layer bounce buffers

mtip32xx just sets the block bounce limit to the dma mask, which means that the iommu or swiotlb already take care of the bounce buffering, and the block bouncing can be removed. Signed-off-by: Christoph Hellwig --- drivers/block/mtip32xx/mtip32xx.c | 1 - 1 file changed, 1

remove PCI_DMA_BUS_IS_PHYS

Hi all, this series tries to get rid of the global and PCI_DMA_BUS_IS_PHYS flag, which causes the block layer and networking code to bounce buffer memory above the dma mask in some cases. It is a leftover from i386 + highmem days and is obsolete now that we have swiotlb or iommus so that the dma

[PATCH 02/12] storsvc: don't set a bounce limit

The default already is to never bounce, so the call is a no-op. Signed-off-by: Christoph Hellwig --- drivers/scsi/storvsc_drv.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/scsi/storvsc_drv.c b/drivers/scsi/storvsc_drv.c index 8c51d628b52e..5f2d177c3bd9 100644 ---