On Tue, Sep 11, 2018 at 10:42:09AM +0800, Kenneth Lee wrote:
> On Mon, Sep 10, 2018 at 10:54:23AM -0400, Jerome Glisse wrote:
> > On Mon, Sep 10, 2018 at 11:28:09AM +0800, Kenneth Lee wrote:
> > > On Fri, Sep 07, 2018 at 12:53:06PM -0400, Jerome Glisse wrote:
> > > > On Fri, Sep 07, 2018 at
On Mon, Sep 10, 2018 at 10:54:23AM -0400, Jerome Glisse wrote:
> Date: Mon, 10 Sep 2018 10:54:23 -0400
> From: Jerome Glisse
> To: Kenneth Lee
> CC: Kenneth Lee , Alex Williamson
> , Herbert Xu ,
> k...@vger.kernel.org, Jonathan Corbet , Greg Kroah-Hartman
> , Joerg Roedel ,
>
Hi Jacob,
On 09/10/2018 07:50 PM, Jacob Pan wrote:
> On Mon, 10 Sep 2018 16:52:24 +0200
> Auger Eric wrote:
>
>> Hi Jacob,
>>
> Hi Eric,
>
> Thanks for the review, please comments inline.
>> On 05/11/2018 10:54 PM, Jacob Pan wrote:
>>> IO page faults can be handled outside IOMMU subsystem. For
On Thu, 30 Aug 2018 20:15:40 +0530, Vivek Gautam wrote:
> Add bindings doc for Qcom's smmu-v2 implementation.
>
> Signed-off-by: Vivek Gautam
> Reviewed-by: Tomasz Figa
> Tested-by: Srinivas Kandagatla
> ---
> .../devicetree/bindings/iommu/arm,smmu.txt | 39
> ++
>
On Mon, 10 Sep 2018 16:52:24 +0200
Auger Eric wrote:
> Hi Jacob,
>
Hi Eric,
Thanks for the review, please comments inline.
> On 05/11/2018 10:54 PM, Jacob Pan wrote:
> > IO page faults can be handled outside IOMMU subsystem. For an
> > example, when nested translation is turned on and guest
On 30/08/2018 05:09, Lu Baolu wrote:
> +static int vfio_detach_aux_domain(struct device *dev, void *data)
> +{
> + struct iommu_domain *domain = data;
> +
> + vfio_mdev_set_aux_domain(dev, NULL);
> + iommu_detach_device(domain, dev->parent);
I think that's only going to work for vt-d,
Hi,
On 30/08/2018 05:09, Lu Baolu wrote:
> Below APIs are introduced in the IOMMU glue for device drivers to use
> the finer granularity translation.
>
> * iommu_capable(IOMMU_CAP_AUX_DOMAIN)
> - Represents the ability for supporting multiple domains per device
> (a.k.a. finer granularity
On Mon, Sep 10, 2018 at 08:05:30AM +0200, Christoph Hellwig wrote:
> diff --git a/include/linux/device.h b/include/linux/device.h
> index 8f882549edee..983506789402 100644
> --- a/include/linux/device.h
> +++ b/include/linux/device.h
> @@ -927,6 +927,8 @@ struct dev_links_info {
> * @offline:
On 10/09/18 16:47, Christoph Hellwig wrote:
--- a/kernel/dma/Kconfig
+++ b/kernel/dma/Kconfig
@@ -13,6 +13,9 @@ config NEED_DMA_MAP_STATE
config ARCH_DMA_ADDR_T_64BIT
def_bool 64BIT || PHYS_ADDR_T_64BIT
+config ARCH_HAS_DMA_COHERENCE_H
+ bool
This seems a little crude - is
On Mon, Sep 10, 2018 at 04:19:30PM +0100, Robin Murphy wrote:
>> +#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
>> +defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
>> +defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
>
> If we're likely to refer to it more than once, is it worth
On 10/09/18 07:05, Christoph Hellwig wrote:
Various architectures support both coherent and non-coherent dma on a
per-device basis. Move the dma_noncoherent flag from the mips archdata
field to struct device proper to prepare the infrastructure for reuse on
other architectures.
Signed-off-by:
Hi Jean-Philippe,
On 05/11/2018 09:06 PM, Jean-Philippe Brucker wrote:
> When removing a mapping from a domain, we need to send an invalidation to
> all devices that might have stored it in their Address Translation Cache
> (ATC). In addition when updating the context descriptor of a live domain,
On Mon, Sep 10, 2018 at 11:28:09AM +0800, Kenneth Lee wrote:
> On Fri, Sep 07, 2018 at 12:53:06PM -0400, Jerome Glisse wrote:
> > On Fri, Sep 07, 2018 at 12:01:38PM +0800, Kenneth Lee wrote:
> > > On Thu, Sep 06, 2018 at 09:31:33AM -0400, Jerome Glisse wrote:
> > > > On Thu, Sep 06, 2018 at
Hi Jacob,
On 05/11/2018 10:54 PM, Jacob Pan wrote:
> IO page faults can be handled outside IOMMU subsystem. For an example,
> when nested translation is turned on and guest owns the
> first level page tables, device page request can be forwared
forwarded
> to the guest for handling faults. As the
On 10/09/18 15:07, Meelis Roos wrote:
Given the __alloc_pages_slowpath() warning, this looks like it's probably
stemming from the oversized PASID table issue which a few other folks have hit
too. I think this patch is the most up-to-date fix:
Am Freitag, 31. August 2018, 00:28:32 CEST schrieb Ezequiel Garcia:
> Printing verbosely via WARN macros and friends in interrupt handlers
> is strongly discouraged. Drop them and use proper ratelimited
> prints.
>
> Signed-off-by: Ezequiel Garcia
Reviewed-by: Heiko Stuebner
> Given the __alloc_pages_slowpath() warning, this looks like it's probably
> stemming from the oversized PASID table issue which a few other folks have hit
> too. I think this patch is the most up-to-date fix:
>
> https://www.mail-archive.com/iommu@lists.linux-foundation.org/msg25639.html
The
fsl-mc bus support the new iommu-map property. Comply to this binding
for fsl_mc bus.
Signed-off-by: Nipun Gupta
Reviewed-by: Laurentiu Tudor
---
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
of_dma_configure() API expects coherent_dma_mask to be correctly
set in the devices. This patch does the needful.
Signed-off-by: Nipun Gupta
Reviewed-by: Robin Murphy
---
drivers/bus/fsl-mc/fsl-mc-bus.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c
The existing IOMMU bindings cannot be used to specify the relationship
between fsl-mc devices and IOMMUs. This patch adds a generic binding for
mapping fsl-mc devices to IOMMUs, using iommu-map property.
Signed-off-by: Nipun Gupta
Reviewed-by: Rob Herring
Acked-by: Robin Murphy
---
iommu-map property is also used by devices with fsl-mc. This
patch moves the of_pci_map_rid to generic location, so that it
can be used by other busses too.
'of_pci_map_rid' is renamed here to 'of_map_rid' and there is no
functional change done in the API.
Signed-off-by: Nipun Gupta
This patch adds support of dma configuration for devices on fsl-mc
bus using 'dma_configure' callback for busses. Also, directly calling
arch_setup_dma_ops is removed from the fsl-mc bus.
Signed-off-by: Nipun Gupta
Reviewed-by: Laurentiu Tudor
Reviewed-by: Robin Murphy
---
Implement bus specific support for the fsl-mc bus including
registering arm_smmu_ops and bus specific device add operations.
Signed-off-by: Nipun Gupta
Reviewed-by: Robin Murphy
---
drivers/iommu/arm-smmu.c | 7 +++
drivers/iommu/iommu.c| 13 +
include/linux/fsl/mc.h |
With of_pci_map_rid available for all the busses, use the function
for configuration of devices on fsl-mc bus
Signed-off-by: Nipun Gupta
Reviewed-by: Robin Murphy
---
drivers/iommu/of_iommu.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/iommu/of_iommu.c
This patchset defines IOMMU DT binding for fsl-mc bus and adds
support in SMMU for fsl-mc bus.
These patches
- Define property 'iommu-map' for fsl-mc bus (patch 1)
- Integrates the fsl-mc bus with the SMMU using this
IOMMU binding (patch 2,3,4)
- Adds the dma configuration support for
On 10/09/18 14:23, Christoph Hellwig wrote:
On Mon, Sep 10, 2018 at 11:16:12AM +0300, Meelis Roos wrote:
In 4.19-rc1, I found that to keep Intel integrated graphics working when
VT-d is on, I need to have IOMMU passthough on or GPU init would fail
with DMAR error and the screen would display
On Mon, Sep 10, 2018 at 11:16:12AM +0300, Meelis Roos wrote:
> In 4.19-rc1, I found that to keep Intel integrated graphics working when
> VT-d is on, I need to have IOMMU passthough on or GPU init would fail
> with DMAR error and the screen would display static gibberish. So I
> turned IOMMU PT
+linux-arm-msm
On 09/10/2018 11:55 AM, Vivek Gautam wrote:
Qcom's implementation of arm,mmu-500 on sdm845 has a functional/performance
errata [1] because of which the TCU cache look ups are stalled during
invalidation cycle. This is mitigated by serializing all the invalidation
requests coming
In 4.19-rc1, I found that to keep Intel integrated graphics working when
VT-d is on, I need to have IOMMU passthough on or GPU init would fail
with DMAR error and the screen would display static gibberish. So I
turned IOMMU PT on by default in kernel config. It worked, also in rc2.
Now with
Qcom's implementation of arm,mmu-500 on sdm845 has a functional/performance
errata [1] because of which the TCU cache look ups are stalled during
invalidation cycle. This is mitigated by serializing all the invalidation
requests coming to the smmu.
This patch series addresses this errata by
Add atomic versions of qcom_scm_io_readl/writel to enable
reading/writing secure registers from atomic context.
Signed-off-by: Vivek Gautam
---
drivers/firmware/qcom_scm-32.c | 12
drivers/firmware/qcom_scm-64.c | 32
drivers/firmware/qcom_scm.c
Qcom's implementation of arm,mmu-500 require to serialize all
TLB invalidations for context banks.
In case the TLB invalidation requests don't go through the first
time, there's a way to disable/enable the wait for safe logic.
Disabling this logic expadites the TLBIs.
Different bootloaders with
Qcom's smmu-500 needs to toggle wait-for-safe sequence to
handle TLB invalidation sync's.
Few firmwares allow doing that through SCM interface.
Add API to toggle wait for safe from firmware through a
SCM call.
Signed-off-by: Vivek Gautam
---
drivers/firmware/qcom_scm-32.c | 5 +
There are scnenarios where drivers are required to make a
scm call in atomic context, such as in one of the qcom's
arm-smmu-500 errata [1].
[1] ("https://source.codeaurora.org/quic/la/kernel/msm-4.9/
tree/drivers/iommu/arm-smmu.c?h=msm-4.9#n4842")
Signed-off-by: Vivek Gautam
---
This save some duplication for ia64. In the long run this method will
need some additional work including moving over to kernel/dma, but that
will require some additional prep work, so let's do this minimal change
for now.
Signed-off-by: Christoph Hellwig
---
If we use fls64 we don't need to divide the max address into lower
and upper halves.
Signed-off-by: Christoph Hellwig
---
drivers/base/platform.c | 18 +++---
1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index
Hi all,
the dma_get_required_mask dma API implementation has always been a little
odd, in that we by default don't wire it up struct dma_map_ops, but
instead hard code a default implementation. powerpc and ia64 override
this default and either call a method or otherwise duplicate the default.
We need to apply an DMA offset for the function to work as expected.
Signed-off-by: Christoph Hellwig
---
drivers/base/platform.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index 7812b861b6da..6feac7294f8d 100644
---
We can use the arch_dma_coherent_to_pfn hook to provide a ->get_sgtable
implementation. Note that this isn't an endorsement of this interface
(which is a horrible bad idea), but it is required to move arm64 over
to the generic code without a loss of functionality.
Signed-off-by: Christoph
All the cache maintainance is already stubbed out when not enabled,
but merging the two allows us to nicely handle the case where
cache maintainance is required for some devices, but not others.
Signed-off-by: Christoph Hellwig
Acked-by: Paul Burton # MIPS parts
---
arch/arc/Kconfig
The only functional differences (modulo a few missing fixes in the arch
code) is that architectures without coherent caches need a hook to
convert a virtual or dma address into a pfn, given that we don't have
the kernel linear mapping available for the otherwise easy virt_to_page
call. As a side
Various architectures support both coherent and non-coherent dma on a
per-device basis. Move the dma_noncoherent flag from the mips archdata
field to struct device proper to prepare the infrastructure for reuse on
other architectures.
Signed-off-by: Christoph Hellwig
Acked-by: Paul Burton
---
While most architectures are either always or never dma coherent for a
given build, the arm, arm64, mips and soon arc architectures can have
different dma coherent settings on a per-device basis. Additionally
some mips builds can decide at boot time if dma is coherent or not.
I've started to
While both option select a form of conditional dma coherence they don't
actually share any code in the implementation, so untangle them.
Signed-off-by: Christoph Hellwig
Acked-by: Paul Burton
---
arch/mips/Kconfig| 2 +-
arch/mips/kernel/setup.c | 2 +-
arch/mips/mm/c-r4k.c | 17
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