On 2018-12-12 11:16, Srinath Mannam wrote:
IPROC host has the limitation that it can use
only those address ranges given by dma-ranges
property as inbound address.
So that the memory address holes in dma-ranges
should be reserved to allocate as DMA address.
All such reserved addresses are
On Fri, Dec 7, 2018 at 6:25 PM Vivek Gautam wrote:
>
> Hi Robin,
>
> On Tue, Dec 4, 2018 at 8:51 PM Robin Murphy wrote:
> >
> > On 04/12/2018 11:01, Vivek Gautam wrote:
> > > Qualcomm SoCs have an additional level of cache called as
> > > System cache, aka. Last level cache (LLC). This cache
On Wed, 2018-12-12 at 13:39 +, Robin Murphy wrote:
> On 12/12/2018 13:02, Yong Wu wrote:
> > If CONFIG_RANDOMIZE_BASE is enabled, the "memstart_addr" will be updated
> > randomly, then the PHYS_OFFSET may be random.
>
> Oh, I hadn't ever realised that, good catch. However, since 29859aeb8a6e
There could be unlimited number of allocated domains, but only one domain
can be active at a time. Hence devices must be detached only from the
active domain.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
drivers/iommu/tegra-gart.c | 8 +---
1 file changed, 5 insertions(+), 3
GART is a simple IOMMU provider that has single address space. There is
no need to setup global clients list and manage it for tracking of the
active domain, hence lot's of code could be safely removed and replaced
with a simpler alternative.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry
Removed redundant safety-checks in the code and some debug code that
isn't actually very useful for debugging, like enormous pagetable dump
on each fault. The majority of the changes are code reshuffling,
variables/whitespaces clean up and removal of debug messages that
duplicate messages of the
GART became a part of Memory Controller, hence now the drivers device
is Memory Controller and not GART. As a result all printed messages are
prepended with the "tegra-mc 7000f000.memory-controller:", so let's
prepend GART's messages with "gart:" in order to differentiate them
from the MC.
GART has a single address space that is shared by all devices, hence only
one domain could be active at a time.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
drivers/iommu/tegra-gart.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/iommu/tegra-gart.c
Fix NULL pointer dereference on IOMMU domain destruction that happens
because clients list is being iterated unsafely and its elements are
getting deleted during the iteration.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
drivers/iommu/tegra-gart.c | 4 ++--
1 file changed, 2
Fix spinlock recursion bug that happens on IOMMU domain destruction if
any of the allocated domains have devices attached to them.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
drivers/iommu/tegra-gart.c | 24
1 file changed, 16 insertions(+), 8
Memory Controller driver never shared IRQ with any other driver and very
unlikely that it will. Hence there is no need to request IRQ sharing and
the corresponding flag can be dropped safely.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 2 +-
1 file changed, 1 insertion(+), 1
Make all messages to start with a lower case and don't unnecessarily go
over 80 chars in the code.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/memory/tegra/mc.c
Tegra20 doesn't have SMMU. Move out checking of the SMMU presence from
the SMMU driver into the Memory Controller driver. This change makes code
consistent in regards to how GART/SMMU presence checking is performed.
Signed-off-by: Dmitry Osipenko
---
drivers/iommu/tegra-smmu.c | 4
The device-tree binding has been changed. There is no separate GART device
anymore, it is squashed into the Memory Controller. Integrate GART module
with the MC in a way it is done for the SMMU on Tegra30+.
Signed-off-by: Dmitry Osipenko
---
drivers/iommu/Kconfig | 1 +
There is no need for inserting of memory barriers to access registers of
Memory Controller. Hence use the relaxed versions of the accessors.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
drivers/memory/tegra/mc.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
With the device tree binding changes, now Memory Controller has access to
GART registers. Hence it is now possible to read client ID on GART page
fault to get information about what memory client causes the fault.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
There is no need to match device with the DT node since it was already
matched, use of_device_get_match_data() helper to get the match-data.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
drivers/memory/tegra/mc.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff
The tegra20-mc device-tree binding has been changed, GART has been
squashed into Memory Controller and now the clock property is mandatory
for Tegra20, the DT compatible has been changed as well. Adapt driver to
the DT changes.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
timings for RAM code 0 registered" warning message during of kernels
boot-up on Tegra20.
Fixes: a8d502fd3348 ("memory: tegra: Squash tegra20-mc into common tegra-mc
driver")
Signed-off-by: Dmitry Osipenko
Acked-by: Jon Hunter
Device tree binding of Memory Controller has been changed: GART has been
squashed into the MC, there are a new mandatory clock and #iommu-cells
properties, the compatible has been changed to 'tegra20-mc-gart'.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
Splitting GART and Memory Controller wasn't a good decision that was made
back in the day. Given that the GART driver wasn't ever been used by
anything in the kernel, we decided that it will be better to correct the
mistakes of the past and merge two bindings into a single one. As a result
there
Introduce iotlb_sync_map() callback that is invoked in the end of
iommu_map(). This new callback allows IOMMU drivers to avoid syncing
after mapping of each contiguous chunk and sync only when the whole
mapping is completed, optimizing performance of the mapping operation.
Signed-off-by: Dmitry
GART can't handle all devices, hence ignore devices that aren't related
to GART. IOMMU phandle must be explicitly assign to devices in the device
tree.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
drivers/iommu/tegra-gart.c | 14 +-
1 file changed, 13 insertions(+),
Properly clean up allocated resources on the drivers probe failure and
remove unneeded checks.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
drivers/iommu/tegra-gart.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/tegra-gart.c
Currently GART writes one page entry at a time. More optimal would be to
aggregate the writes and flush BUS buffer in the end, this gives map/unmap
10-40% performance boost (depending on size of mapping) in comparison to
flushing after each page entry update.
Signed-off-by: Dmitry Osipenko
Hello,
This patch-series integrates the GART (IOMMU) driver with the Memory
Controller driver, that allows to report the name of a faulty memory
client on GART page fault. A major code clean up and performance
optimization is performed in this series as well.
Changelog:
v7: Addressed review
Remove unneeded headers inclusion and sort the headers in alphabet order.
Remove pr_fmt macro since there is no pr_*() in the code and it doesn't
affect dev_*() functions.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
drivers/iommu/tegra-gart.c | 17 +
1 file
Hi,
On 12/12/18 3:56 PM, Michael S. Tsirkin wrote:
> On Fri, Dec 07, 2018 at 06:52:31PM +, Jean-Philippe Brucker wrote:
>> Sorry for the delay, I wanted to do a little more performance analysis
>> before continuing.
>>
>> On 27/11/2018 18:10, Michael S. Tsirkin wrote:
>>> On Tue, Nov 27, 2018
On Fri, Dec 07, 2018 at 06:52:31PM +, Jean-Philippe Brucker wrote:
> Sorry for the delay, I wanted to do a little more performance analysis
> before continuing.
>
> On 27/11/2018 18:10, Michael S. Tsirkin wrote:
> > On Tue, Nov 27, 2018 at 05:55:20PM +, Jean-Philippe Brucker wrote:
>
Hi Christoph,
Thanks a lot for your reply. I will test your patches tomorrow.
Cheers,
Christian
Sent from my iPhone
> On 12. Dec 2018, at 15:15, Christoph Hellwig wrote:
>
> Thanks for bisecting. I've spent some time going over the conversion
> but can't really pinpoint it. I have three
On Sun, Dec 09, 2018 at 09:23:39PM +1100, Michael Ellerman wrote:
> Christoph Hellwig writes:
>
> > Configure the dma settings at device setup time, and stop playing games
> > with get_pci_dma_ops. This prepares for using the common dma_configure
> > code later on.
> >
> > Signed-off-by:
On Wed, Dec 12, 2018 at 11:35:45AM +0100, Joerg Roedel wrote:
> Hi,
>
> to make progress on this, we should first agree on the protocol used
> between guest and host. I have a few points to discuss on the protocol
> first.
>
> On Tue, Dec 11, 2018 at 06:20:57PM +, Jean-Philippe Brucker
Thanks for bisecting. I've spent some time going over the conversion
but can't really pinpoint it. I have three little patches that switch
parts of the code to the generic version. This is on top of the
last good commmit (977706f9755d2d697aa6f45b4f9f0e07516efeda).
Can you check with whіch one
On 12.12.2018 13:14, Thierry Reding wrote:
> On Sun, Dec 09, 2018 at 11:29:42PM +0300, Dmitry Osipenko wrote:
>> The device-tree binding has been changed. There is no separate GART device
>> anymore, it is squashed into the Memory Controller. Integrate GART module
>> with the MC in a way it is
On Tue, 2018-12-11 at 13:19 +0100, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Use the new helpers dev_iommu_fwspec_get()/set() to access
> the dev->iommu_fwspec pointer. This makes it easier to move
> that pointer later into another struct.
>
> Cc: Matthias Brugger
> Signed-off-by: Joerg
On 12/12/2018 13:02, Yong Wu wrote:
If CONFIG_RANDOMIZE_BASE is enabled, the "memstart_addr" will be updated
randomly, then the PHYS_OFFSET may be random.
Oh, I hadn't ever realised that, good catch. However, since 29859aeb8a6e
I think we should probably just remove this check altogether.
If CONFIG_RANDOMIZE_BASE is enabled, the "memstart_addr" will be updated
randomly, then the PHYS_OFFSET may be random.
Fixes: 82db33dc5e49 ("iommu/io-pgtable-arm: Check for v7s-incapable
systems")
Reported-by: CK Hu
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 2 +-
1 file
On 12.12.2018 13:43, Joerg Roedel wrote:
> Hi Thierry, Hi Dmitry,
>
> On Wed, Dec 12, 2018 at 11:24:15AM +0100, Thierry Reding wrote:
>> So appart from the one issue in the "memory controller integration"
>> patch this looks good and I've acked the remaining patches. Once the one
>> remaining
On Wed, Dec 12, 2018 at 12:04:35PM +0100, Greg Kroah-Hartman wrote:
> On Tue, Dec 11, 2018 at 02:43:38PM +0100, Joerg Roedel wrote:
> > Cc: Greg Kroah-Hartman
> > Acked-by: Greg Kroah-Hartman
>
> No need to have a cc: line if I have already acked it :)
Right, I'll remove it, sorry for the
On Tue, Dec 11, 2018 at 02:43:38PM +0100, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Some places in the kernel check the iommu_group pointer in
> 'struct device' in order to find ot whether a device is
> mapped by an IOMMU.
>
> This is not good way to make this check, as the pointer will
> be
Hi Thierry, Hi Dmitry,
On Wed, Dec 12, 2018 at 11:24:15AM +0100, Thierry Reding wrote:
> So appart from the one issue in the "memory controller integration"
> patch this looks good and I've acked the remaining patches. Once the one
> remaining issue is fixed I think this is ready to be merged.
>
Hi,
to make progress on this, we should first agree on the protocol used
between guest and host. I have a few points to discuss on the protocol
first.
On Tue, Dec 11, 2018 at 06:20:57PM +, Jean-Philippe Brucker wrote:
> [1] Virtio-iommu specification v0.9, sources and pdf
>
On Tue, Dec 11, 2018 at 10:53:17AM +0100, Joerg Roedel wrote:
> On Sun, Dec 09, 2018 at 11:29:29PM +0300, Dmitry Osipenko wrote:
> > Dmitry Osipenko (21):
> > iommu/tegra: gart: Remove pr_fmt and clean up includes
> > iommu/tegra: gart: Clean up driver probe errors handling
> > iommu/tegra:
On Sun, Dec 09, 2018 at 11:29:47PM +0300, Dmitry Osipenko wrote:
> GART became a part of Memory Controller, hence now the drivers device
> is Memory Controller and not GART. As a result all printed messages are
> prepended with the "tegra-mc 7000f000.memory-controller:", so let's
> prepend GART's
On Sun, Dec 09, 2018 at 11:29:50PM +0300, Dmitry Osipenko wrote:
> Removed redundant safety-checks in the code and some debug code that
> isn't actually very useful for debugging, like enormous pagetable dump
> on each fault. The majority of the changes are code reshuffling,
>
On Sun, Dec 09, 2018 at 11:29:39PM +0300, Dmitry Osipenko wrote:
> With the device tree binding changes, now Memory Controller has access to
> GART registers. Hence it is now possible to read client ID on GART page
> fault to get information about what memory client causes the fault.
>
>
On Sun, Dec 09, 2018 at 11:29:40PM +0300, Dmitry Osipenko wrote:
> There is no need to match device with the DT node since it was already
> matched, use of_device_get_match_data() helper to get the match-data.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/mc.c | 8 ++--
>
> From: 'j...@8bytes.org' [mailto:j...@8bytes.org]
> Sent: Wednesday, December 12, 2018 5:54 PM
>
> Hi Kevin,
>
> On Wed, Dec 12, 2018 at 09:31:27AM +, Tian, Kevin wrote:
> > > From: 'j...@8bytes.org'
> > > Sent: Monday, December 10, 2018 4:58 PM
> > > These represent whether the device
On Sun, Dec 09, 2018 at 11:29:38PM +0300, Dmitry Osipenko wrote:
> The tegra20-mc device-tree binding has been changed, GART has been
> squashed into Memory Controller and now the clock property is mandatory
> for Tegra20, the DT compatible has been changed as well. Adapt driver to
> the DT
On Sun, Dec 09, 2018 at 11:29:37PM +0300, Dmitry Osipenko wrote:
> This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
> timings for RAM code 0 registered" warning message during of kernels
> boot-up on Tegra20.
>
> Fixes: a8d502fd3348 ("memory: tegra: Squash tegra20-mc into
On Sun, Dec 09, 2018 at 11:29:36PM +0300, Dmitry Osipenko wrote:
> Device tree binding of Memory Controller has been changed: GART has been
> squashed into the MC, there are a new mandatory clock and #iommu-cells
> properties, the compatible has been changed to 'tegra20-mc-gart'.
>
>
On Sun, Dec 09, 2018 at 11:29:35PM +0300, Dmitry Osipenko wrote:
> Splitting GART and Memory Controller wasn't a good decision that was made
> back in the day. Given that the GART driver wasn't ever been used by
> anything in the kernel, we decided that it will be better to correct the
> mistakes
On Tue, Dec 11, 2018 at 01:19:10PM +0100, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Use the new helpers dev_iommu_fwspec_get()/set() to access
> the dev->iommu_fwspec pointer. This makes it easier to move
> that pointer later into another struct.
>
> Cc: Thierry Reding
> Signed-off-by:
Hi Will,
On Fri, Oct 12, 2018 at 11:37 AM Vivek Gautam
wrote:
>
>
>
> On 10/12/2018 3:46 AM, Rob Herring wrote:
> > On Thu, 11 Oct 2018 15:19:29 +0530, Vivek Gautam wrote:
> >> Qcom's implementation of arm,mmu-500 works well with current
> >> arm-smmu driver implementation. Adding a soc specific
> From: 'j...@8bytes.org'
> Sent: Monday, December 10, 2018 4:58 PM
>
> Hi Kevin,
>
> On Mon, Dec 10, 2018 at 02:06:44AM +, Tian, Kevin wrote:
> > Can I interpret above as that you agree with the aux domain concept (i.e.
> one
> > device can be linked to multiple domains) in general, and now
On Tue, Dec 11, 2018 at 01:35:23PM +, Jean-Philippe Brucker wrote:
> > /* So we need a iommu_aux_detach_all()? */
>
> This could be useful for device drivers that want to do bulk cleanup on
> device removal. If they rely on Function Level Reset to disable PASID
> states for example, they
On Tue, Dec 11, 2018 at 06:34:23PM +, Jean-Philippe Brucker wrote:
> The cost of enabling those features for a device does seem negligible.
> For the SMMU we need to allocate about 70k of additional memory for the
> initial PASID table, but enabling the PASID cap shouldn't add any
> overhead
On Tue, Dec 11, 2018 at 08:08:48PM +, Will Deacon wrote:
> The following changes since commit 9ff01193a20d391e8dbce4403dd5ef87c7eaaca6:
>
> Linux 4.20-rc3 (2018-11-18 13:33:44 -0800)
>
> are available in the git repository at:
>
>
Hi Jacob,
On 9/21/18 12:06 AM, Jacob Pan wrote:
> On Tue, 18 Sep 2018 16:24:51 +0200
> Eric Auger wrote:
>
>> From: Jacob Pan
>>
>> Device faults detected by IOMMU can be reported outside IOMMU
>> subsystem for further processing. This patch intends to provide
>> a generic device fault data
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