Hi Robin, Lorenzo,
Thanks for review and guidance.
AFAIU, conclusion of discussion is, to return error if dma-ranges list
is not sorted.
So that, Can I send a new patch with below change to return error if
dma-ranges list is not sorted?
-static void iova_reserve_pci_windows(struct pci_dev *dev,
Hi David,
Thanks for review, I will fix in next version of this patch set.
Regards,
Srinath.
On Thu, May 2, 2019 at 3:24 PM David Laight wrote:
>
> From: Srinath Mannam
> > Sent: 01 May 2019 16:23
> ...
> > > > On Fri, Apr 12, 2019 at 08:43:32AM +0530, Srinath Mannam wrote:
> > > > > Few SOCs h
On Thu, 2 May 2019 11:53:34 +0100
Jean-Philippe Brucker wrote:
> On 02/05/2019 07:58, Auger Eric wrote:
> > Hi Jean-Philippe,
> >
> > On 5/1/19 12:38 PM, Jean-Philippe Brucker wrote:
> >> On 08/04/2019 13:18, Eric Auger wrote:
> >>> +int iommu_cache_invalidate(struct iommu_domain *domain, st
On 02/05/2019 14:06, Lorenzo Pieralisi wrote:
On Thu, May 02, 2019 at 12:27:02PM +0100, Robin Murphy wrote:
Hi Lorenzo,
On 02/05/2019 12:01, Lorenzo Pieralisi wrote:
On Wed, May 01, 2019 at 11:06:25PM +0530, Srinath Mannam wrote:
dma_ranges field of PCI host bridge structure has resource entr
On Tue, Apr 30, 2019 at 04:24:21PM +0100, Catalin Marinas wrote:
> My reading of the arm32 __dma_alloc() is that if the conditions are
> right for the CMA allocator (allows blocking) and there is a default CMA
> area or a per-device one, the call ends up in cma_alloc() without any
> fallback if suc
Hi Catalin and Will,
can you quickly look over the arm64 parts? I'd really like to still
get this series in for this merge window as it would conflict with
a lot of dma-mapping work for next merge window, and we also have
the amd and possibly intel iommu conversions to use it waiting.
On Tue, Ap
On Thu, May 02, 2019 at 12:08:01AM +, Paul Burton wrote:
> > Can you test the stack with the two updated patches and ack them if
> > they are fine? That would allow getting at least the infrastructure
> > and mips in for this merge window.
>
> Did you send a v2 of this patch?
>
> If so it ha
On Thu, May 02, 2019 at 12:27:02PM +0100, Robin Murphy wrote:
> Hi Lorenzo,
>
> On 02/05/2019 12:01, Lorenzo Pieralisi wrote:
> > On Wed, May 01, 2019 at 11:06:25PM +0530, Srinath Mannam wrote:
> > > dma_ranges field of PCI host bridge structure has resource entries in
> > > sorted order of addres
On Thu, 2019-05-02 at 12:58 +, Laurentiu Tudor wrote:
>
> > -Original Message-
> > From: Joakim Tjernlund
> > Sent: Thursday, May 2, 2019 1:37 PM
> >
> > On Thu, 2019-05-02 at 09:05 +, Laurentiu Tudor wrote:
> > > Hi Joakim,
> > >
> > > > -Original Message-
> > > > From:
> -Original Message-
> From: Joakim Tjernlund
> Sent: Thursday, May 2, 2019 1:37 PM
>
> On Thu, 2019-05-02 at 09:05 +, Laurentiu Tudor wrote:
> > Hi Joakim,
> >
> > > -Original Message-
> > > From: Joakim Tjernlund
> > > Sent: Saturday, April 27, 2019 8:11 PM
> > >
> > > O
Hi Lorenzo,
On 02/05/2019 12:01, Lorenzo Pieralisi wrote:
On Wed, May 01, 2019 at 11:06:25PM +0530, Srinath Mannam wrote:
dma_ranges field of PCI host bridge structure has resource entries in
sorted order of address range given through dma-ranges DT property. This
list is the accessible DMA add
On Wed, May 01, 2019 at 11:06:25PM +0530, Srinath Mannam wrote:
> dma_ranges field of PCI host bridge structure has resource entries in
> sorted order of address range given through dma-ranges DT property. This
> list is the accessible DMA address range. So that this resource list will
> be process
On 02/05/2019 07:58, Auger Eric wrote:
> Hi Jean-Philippe,
>
> On 5/1/19 12:38 PM, Jean-Philippe Brucker wrote:
>> On 08/04/2019 13:18, Eric Auger wrote:
>>> +int iommu_cache_invalidate(struct iommu_domain *domain, struct device *dev,
>>> + struct iommu_cache_invalidate_info *
On Thu, 2019-05-02 at 09:05 +, Laurentiu Tudor wrote:
> Hi Joakim,
>
> > -Original Message-
> > From: Joakim Tjernlund
> > Sent: Saturday, April 27, 2019 8:11 PM
> >
> > On Sat, 2019-04-27 at 10:10 +0300, laurentiu.tu...@nxp.com wrote:
> > > From: Laurentiu Tudor
> > >
> > > Fix is
From: Srinath Mannam
> Sent: 01 May 2019 16:23
...
> > > On Fri, Apr 12, 2019 at 08:43:32AM +0530, Srinath Mannam wrote:
> > > > Few SOCs have limitation that their PCIe host can't allow few inbound
> > > > address ranges. Allowed inbound address ranges are listed in dma-ranges
> > > > DT property
> -Original Message-
> From: Christoph Hellwig
> Sent: Saturday, April 27, 2019 7:46 PM
>
> On Sat, Apr 27, 2019 at 10:10:29AM +0300, laurentiu.tu...@nxp.com wrote:
> > From: Laurentiu Tudor
> >
> > The driver relies on the no longer valid assumption that dma addresses
> > (iovas) are
Hi Joakim,
> -Original Message-
> From: Joakim Tjernlund
> Sent: Saturday, April 27, 2019 8:11 PM
>
> On Sat, 2019-04-27 at 10:10 +0300, laurentiu.tu...@nxp.com wrote:
> > From: Laurentiu Tudor
> >
> > Fix issue with the entry indexing in the sg frame cleanup code being
> > off-by-1. Th
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