> > static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu,
> > u16
> bus)
> > {
> > struct context_entry *context;
> > - u16 devfn;
> > + u16 devfn, pasid_dir_size;
> > + u64 pasid_dir_ptr;
> >
> > for (devfn = 0; devfn < 256; devfn++) {
> > struct tb
> Hi Sai,
>
> On 5/10/19 2:41 AM, Sai Praneeth Prakhya wrote:
> > From: Sai Praneeth
> >
> > Presently, "/sys/kernel/debug/iommu/intel/dmar_translation_struct"
> > file dumps only legacy DMAR table which consists of root table and
> > context table. Scalable mode DMAR table adds PASID directory a
Hi Robin,
On 5/10/19 12:11 AM, Robin Murphy wrote:
On 09/05/2019 03:30, Lu Baolu wrote:
Hi Robin,
On 5/7/19 6:28 PM, Robin Murphy wrote:
On 06/05/2019 16:32, Tom Murphy via iommu wrote:
The AMD driver already solves this problem and uses the generic
iommu_request_dm_for_dev function. It seem
Hi,
On 5/10/19 2:42 AM, Sai Praneeth Prakhya wrote:
From: Sai Praneeth
A DMAR table walk would typically follow the below process.
1. Bus number is used to index into root table which points to a context
table.
2. Device number and Function number are used together to index into
contex
Hi,
On 5/10/19 2:42 AM, Sai Praneeth Prakhya wrote:
From: Sai Praneeth
A scalable mode DMAR table walk would involve looking at bits in each stage
of walk, like,
1. Is PASID enabled in the context entry?
2. What's the size of PASID directory?
3. Is the PASID directory entry present?
4. Is the
Hi,
On 5/10/19 2:41 AM, Sai Praneeth Prakhya wrote:
From: Sai Praneeth
Presently, "/sys/kernel/debug/iommu/intel/dmar_translation_struct" file
dumps DMAR tables in the below format
IOMMU dmar2: Root Table Address:4362cc000
Root Table Entries:
Bus: 0 H: 0 L: 4362f0001
Context Table Entries
Hi Sai,
On 5/10/19 2:41 AM, Sai Praneeth Prakhya wrote:
From: Sai Praneeth
Presently, "/sys/kernel/debug/iommu/intel/dmar_translation_struct" file dumps
only legacy DMAR table which consists of root table and context table. Scalable
mode DMAR table adds PASID directory and PASID table. Hence,
From: Sai Praneeth
A DMAR table walk would typically follow the below process.
1. Bus number is used to index into root table which points to a context
table.
2. Device number and Function number are used together to index into
context table which then points to a pasid directory.
3. PASID[
From: Sai Praneeth
A scalable mode DMAR table walk would involve looking at bits in each stage
of walk, like,
1. Is PASID enabled in the context entry?
2. What's the size of PASID directory?
3. Is the PASID directory entry present?
4. Is the PASID table entry present?
5. Number of PASID table ent
From: Sai Praneeth
Presently, "/sys/kernel/debug/iommu/intel/dmar_translation_struct" file
dumps DMAR tables in the below format
IOMMU dmar2: Root Table Address:4362cc000
Root Table Entries:
Bus: 0 H: 0 L: 4362f0001
Context Table Entries for Bus: 0
Entry B:D.F HighLow
160 00:14.0 1
From: Sai Praneeth
Presently, "/sys/kernel/debug/iommu/intel/dmar_translation_struct" file dumps
only legacy DMAR table which consists of root table and context table. Scalable
mode DMAR table adds PASID directory and PASID table. Hence, add support to dump
these tables as well.
Directly extendi
The pull request you sent on Thu, 9 May 2019 09:16:34 +0200:
> git://git.infradead.org/users/hch/dma-mapping.git tags/dma-mapping-5.2
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/ddab5337b23c99777d7cfb39c0f8efe536c17dff
Thank you!
--
Deet-doot-dot, I am a bot.
htt
On 09/05/2019 03:30, Lu Baolu wrote:
Hi Robin,
On 5/7/19 6:28 PM, Robin Murphy wrote:
On 06/05/2019 16:32, Tom Murphy via iommu wrote:
The AMD driver already solves this problem and uses the generic
iommu_request_dm_for_dev function. It seems like both drivers have the
same problem and could u
DMA allocations with the DMA_ATTR_NO_KERNEL_MAPPING do not return a kernel
virtual address for use in driver, but are expected to be used entirely
for userspace mappings and/or device private memory.
Because of that we don't need to remap them as uncached, and thus don't need
the atomic pool for n
Hi Linus,
a pretty small DMA mapping updates for this merge window below:
The following changes since commit 15ade5d2e7775667cf191cf2f94327a4889f8b9d:
Linux 5.1-rc4 (2019-04-07 14:09:59 -1000)
are available in the Git repository at:
git://git.infradead.org/users/hch/dma-mapping.git tags/d
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