RE: [PATCH v4 3/5] iommu/vt-d: Disable non-recoverable fault processing before unbind

> From: Lu Baolu > Sent: Thursday, May 7, 2020 8:56 AM > > When a PASID is used for SVA by the device, it's possible that the PASID > entry is cleared before the device flushes all ongoing DMA requests. The > IOMMU should ignore the non-recoverable faults caused by these requests. > Intel VT-d

RE: [PATCH v4 2/5] iommu/vt-d: debugfs: Add support to show inv queue internals

> From: Lu Baolu > Sent: Thursday, May 7, 2020 8:56 AM > > Export invalidation queue internals of each iommu device through the > debugfs. > > Example of such dump on a Skylake machine: > > $ sudo cat /sys/kernel/debug/iommu/intel/invalidation_queue > Invalidation queue on IOMMU: dmar1 >

RE: [PATCH v4 1/5] iommu/vt-d: Multiple descriptors per qi_submit_sync()

> From: Lu Baolu > Sent: Thursday, May 7, 2020 8:56 AM > > Current qi_submit_sync() only supports single invalidation descriptor > per submission and appends wait descriptor after each submission to > poll the hardware completion. This extends the qi_submit_sync() helper > to support multiple

[PATCH v4 4/5] iommu/vt-d: Add page request draining support

When a PASID is stopped or terminated, there can be pending PRQs (requests that haven't received responses) in remapping hardware. This adds the interface to drain page requests and call it when a PASID is terminated. Signed-off-by: Jacob Pan Signed-off-by: Liu Yi L Signed-off-by: Lu Baolu ---

[PATCH v4 5/5] iommu/vt-d: Remove redundant IOTLB flush

IOTLB flush already included in the PASID tear down and the page request drain process. There is no need to flush again. Signed-off-by: Jacob Pan Signed-off-by: Lu Baolu --- drivers/iommu/intel-svm.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git

[PATCH v4 0/5] iommu/vt-d: Add page request draining support

When a PASID is stopped or terminated, there can be pending PRQs (requests that haven't received responses) in the software and remapping hardware. The pending page requests must be drained so that the pasid could be reused. The chapter 7.10 in the VT-d specification specifies the software steps

[PATCH v4 1/5] iommu/vt-d: Multiple descriptors per qi_submit_sync()

Current qi_submit_sync() only supports single invalidation descriptor per submission and appends wait descriptor after each submission to poll the hardware completion. This extends the qi_submit_sync() helper to support multiple descriptors, and add an option so that the caller could specify the

[PATCH v4 3/5] iommu/vt-d: Disable non-recoverable fault processing before unbind

When a PASID is used for SVA by the device, it's possible that the PASID entry is cleared before the device flushes all ongoing DMA requests. The IOMMU should ignore the non-recoverable faults caused by these requests. Intel VT-d provides such function through the FPD bit of the PASID entry. This

[PATCH v4 2/5] iommu/vt-d: debugfs: Add support to show inv queue internals

Export invalidation queue internals of each iommu device through the debugfs. Example of such dump on a Skylake machine: $ sudo cat /sys/kernel/debug/iommu/intel/invalidation_queue Invalidation queue on IOMMU: dmar1 Base: 0x1672c9000 Head: 80Tail: 80 Index qw0

Re: [PATCHv2] iommu/arm-smmu: Make remove callback message more informative

Hi, On Thu, Apr 23, 2020 at 7:35 AM Doug Anderson wrote: > > Hi, > > On Thu, Apr 23, 2020 at 2:55 AM Sai Prakash Ranjan > wrote: > > > > Currently on reboot/shutdown, the following messages are > > displayed on the console as error messages before the > > system reboots/shutdown as part of

[PATCH] iommu/iova: Retry from last rb tree node if iova search fails

From: Vijayanand Jitta When ever a new iova alloc request comes iova is always searched from the cached node and the nodes which are previous to cached node. So, even if there is free iova space available in the nodes which are next to the cached node iova allocation can still fail because of

Re: [PATCH v4 0/3] Replace private domain with per-group default domain

On Wed, 2020-05-06 at 10:09 +0800, Daniel Drake wrote: > On Wed, May 6, 2020 at 10:03 AM Lu Baolu wrote: > > https://lkml.org/lkml/2020/4/14/616 > > [This has been applied in iommu/next.] > > > > Hence, there is no need to keep the private domain implementation > > in the Intel IOMMU driver.

[PATCH] iommu/arm-smmu-v3: Don't reserve implementation defined register space

Some SMMUv3 implementation embed the Perf Monitor Group Registers (PMCG) inside the first 64kB region of the SMMU. Since PMCG are managed by a separate driver, this layout causes resource reservation conflicts during boot. To avoid this conflict, only reserve the MMIO region we actually use: the

Re: [PATCH] perf/smmuv3: Allow sharing MMIO registers with the SMMU driver

On Wed, Apr 29, 2020 at 11:01:05AM -0700, Tuan Phan wrote: > > > > On Apr 29, 2020, at 12:21 AM, Jean-Philippe Brucker > > wrote: > > > > On Tue, Apr 28, 2020 at 11:10:09AM -0700, Tuan Phan wrote: > >> I tested this patch on HW, however I need to add one more following change > >> to make it

Re: [PATCH] iommu/virtio: reverse arguments to list_add

On Tue, May 05, 2020 at 08:47:47PM +0200, Julia Lawall wrote: > Elsewhere in the file, there is a list_for_each_entry with > >resv_regions as the second argument, suggesting that > >resv_regions is the list head. So exchange the > arguments on the list_add call to put the list head in the >