Re: [PATCH] PCI/ATS: PASID and PRI are only enumerated in PF devices.

2020-07-20 Thread kernel test robot
Hi Ashok, Thank you for the patch! Yet something to improve: [auto build test ERROR on pci/next] [also build test ERROR on iommu/next linux/master linus/master v5.8-rc6 next-20200720] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest

RE: [EXT] Re: [PATCH v2 00/12] ACPI/OF: Upgrade MSI/IOMMU ID mapping APIs

2020-07-20 Thread Makarand Pawagi
> -Original Message- > From: Lorenzo Pieralisi > Sent: Monday, July 20, 2020 10:25 PM > To: linux-arm-ker...@lists.infradead.org; Rob Herring ; > Rafael J. Wysocki ; Bjorn Helgaas ; > Catalin Marinas ; Will Deacon ; > j...@8bytes.org > Cc: Hanjun Guo ; Sudeep Holla > ; Robin Murphy ;

Re: Re: [PATCH 04/21] dt-binding: mediatek: Add binding for mt8192 IOMMU and SMI

2020-07-20 Thread Yong Wu
On Mon, 2020-07-20 at 17:16 -0600, Rob Herring wrote: > On Sat, Jul 11, 2020 at 02:48:29PM +0800, Yong Wu wrote: > > This patch adds decriptions for mt8192 IOMMU and SMI. > > > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > > table format. The M4U-SMI HW diagram is

[PATCH v2] iommu/mediatek: check 4GB mode by reading infracfg

2020-07-20 Thread Miles Chen
In previous discussion [1] and [2], we found that it is risky to use max_pfn or totalram_pages to tell if 4GB mode is enabled. Check 4GB mode by reading infracfg register, remove the usage of the un-exported symbol max_pfn. This is a step towards building mtk_iommu as a kernel module. Change

Re: [PATCH 6/9] dt-bindings: gpio: renesas,rcar-gpio: Add r8a774e1 support

2020-07-20 Thread Rob Herring
On Mon, 13 Jul 2020 22:35:17 +0100, Lad Prabhakar wrote: > Document Renesas RZ/G2H (R8A774E1) GPIO blocks compatibility within the > relevant dt-bindings. > > Signed-off-by: Lad Prabhakar > --- > Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml | 1 + > 1 file changed, 1

Re: [PATCH 8/9] dt-bindings: net: renesas,ravb: Add support for r8a774e1 SoC

2020-07-20 Thread Rob Herring
On Mon, 13 Jul 2020 22:35:19 +0100, Lad Prabhakar wrote: > From: Marian-Cristian Rotariu > > Document RZ/G2H (R8A774E1) SoC bindings. > > Signed-off-by: Marian-Cristian Rotariu > > Signed-off-by: Lad Prabhakar > --- > Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 + > 1 file

Re: [PATCH 1/9] dt-bindings: iommu: renesas, ipmmu-vmsa: Add r8a774e1 support

2020-07-20 Thread Rob Herring
On Mon, Jul 13, 2020 at 10:35:12PM +0100, Lad Prabhakar wrote: > Document RZ/G2H (R8A774E1) SoC bindings. > > Signed-off-by: Lad Prabhakar > --- > Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring

Re: [PATCH 3/9] arm64: dts: renesas: r8a774e1: Add IPMMU device nodes

2020-07-20 Thread Rob Herring
On Mon, Jul 13, 2020 at 10:35:14PM +0100, Lad Prabhakar wrote: > From: Marian-Cristian Rotariu > > Add RZ/G2H (R8A774E1) IPMMU nodes. > > Signed-off-by: Marian-Cristian Rotariu > > Signed-off-by: Lad Prabhakar > --- > arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 121 ++ >

Re: [PATCH v5 2/5] iommu/uapi: Add argsz for user filled data

2020-07-20 Thread Jacob Pan
On Fri, 17 Jul 2020 15:44:23 +0200 Auger Eric wrote: > Hi Jacob, > > On 7/16/20 8:45 PM, Jacob Pan wrote: > > As IOMMU UAPI gets extended, user data size may increase. To support > > backward compatibiliy, this patch introduces a size field to each > > UAPI data structures. It is *always* the

Re: [PATCH v5 1/5] docs: IOMMU user API

2020-07-20 Thread Jacob Pan
On Fri, 17 Jul 2020 13:37:25 -0600 Alex Williamson wrote: > On Thu, 16 Jul 2020 11:45:13 -0700 > Jacob Pan wrote: > > > IOMMU UAPI is newly introduced to support communications between > > guest virtual IOMMU and host IOMMU. There has been lots of > > discussions on how it should work with

RE: [PATCH] iommu/arm-smmu-v3: remove the approach of MSI polling for CMD SYNC

2020-07-20 Thread Song Bao Hua (Barry Song)
> -Original Message- > From: Song Bao Hua (Barry Song) > Sent: Friday, July 17, 2020 9:06 PM > To: 'Robin Murphy' ; w...@kernel.org; > j...@8bytes.org > Cc: linux-ker...@vger.kernel.org; Linuxarm ; > linux-arm-ker...@lists.infradead.org; iommu@lists.linux-foundation.org; > Zengtao (B)

[PATCH 1/1] iommu/vt-d: Skip TE disabling on quirky gfx dedicated iommu

2020-07-20 Thread Lu Baolu
The VT-d spec requires (10.4.4 Global Command Register, TE field) that: Hardware implementations supporting DMA draining must drain any in-flight DMA read/write requests queued within the Root-Complex before completing the translation enable command and reflecting the status of the command

Re: [PATCH v8 00/12] PCI: brcmstb: enable PCIe for STB chips

2020-07-20 Thread Florian Fainelli
On 7/15/20 7:35 AM, Jim Quinlan wrote: > Patchset Summary: > Enhance a PCIe host controller driver. Because of its unusual design > we are foced to change dev->dma_pfn_offset into a more general role > allowing multiple offsets. See the 'v1' notes below for more info. Christoph, Robin,

Re: [PATCH 04/21] dt-binding: mediatek: Add binding for mt8192 IOMMU and SMI

2020-07-20 Thread Rob Herring
On Sat, Jul 11, 2020 at 02:48:29PM +0800, Yong Wu wrote: > This patch adds decriptions for mt8192 IOMMU and SMI. > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > table format. The M4U-SMI HW diagram is as below: > > EMI >

Re: [PATCH v5 1/5] docs: IOMMU user API

2020-07-20 Thread Jacob Pan
Hi Eric, On Fri, 17 Jul 2020 15:32:58 +0200 Auger Eric wrote: > Hi Jacob, > > On 7/16/20 8:45 PM, Jacob Pan wrote: > > IOMMU UAPI is newly introduced to support communications between > > guest virtual IOMMU and host IOMMU. There has been lots of > > discussions on how it should work with VFIO

Re: [PATCH 02/21] dt-binding: memory: mediatek: Extend LARB_NR_MAX to 32

2020-07-20 Thread Rob Herring
On Sat, 11 Jul 2020 14:48:27 +0800, Yong Wu wrote: > Extend the max larb number definition as mt8192 has larb_nr over 16. > > Signed-off-by: Yong Wu > --- > include/dt-bindings/memory/mtk-smi-larb-port.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Acked-by: Rob Herring

Re: [PATCH 01/21] dt-binding: memory: mediatek: Add a common larb-port header file

2020-07-20 Thread Rob Herring
On Sat, 11 Jul 2020 14:48:26 +0800, Yong Wu wrote: > Put all the macros about smi larb/port togethers, this is a preparing > patch for extending LARB_NR and adding new dom-id support. > > Signed-off-by: Yong Wu > --- > include/dt-bindings/memory/mt2712-larb-port.h | 2 +- >

Re: [PATCH] PCI/ATS: PASID and PRI are only enumerated in PF devices.

2020-07-20 Thread kernel test robot
Hi Ashok, Thank you for the patch! Yet something to improve: [auto build test ERROR on pci/next] [also build test ERROR on iommu/next linux/master linus/master v5.8-rc6 next-20200720] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest

Re: [Freedreno] arm64: Internal error: Oops: qcom_iommu_tlb_inv_context free_io_pgtable_ops on db410c

2020-07-20 Thread Naresh Kamboju
On Mon, 20 Jul 2020 at 21:27, Rob Clark wrote: > > On Mon, Jul 20, 2020 at 4:28 AM Robin Murphy wrote: > > > > On 2020-07-20 08:17, Arnd Bergmann wrote: > > > On Mon, Jul 20, 2020 at 8:36 AM Naresh Kamboju > > > wrote: <> > > >> [5.444121] Unable to handle kernel NULL pointer dereference at

Re: [PATCH] iommu/qcom: Use domain rather than dev as tlb cookie

2020-07-20 Thread Naresh Kamboju
On Mon, 20 Jul 2020 at 21:21, Rob Clark wrote: > > From: Rob Clark > > The device may be torn down, but the domain should still be valid. Lets > use that as the tlb flush ops cookie. > > Fixes a problem reported in [1] This proposed fix patch applied on top of linux mainline master and boot

Re: [PATCH v2 00/12] ACPI/OF: Upgrade MSI/IOMMU ID mapping APIs

2020-07-20 Thread Lorenzo Pieralisi
On Fri, Jun 19, 2020 at 09:20:01AM +0100, Lorenzo Pieralisi wrote: > This series is a v2 of a previous posting: > > v1 -> v2 > > - Removed _rid() wrappers > - Fixed !CONFIG_ACPI compilation issue > - Converted of_pci_iommu_init() to use of_iommu_configure_dev_id() > > v1: >

[PATCH] PCI/ATS: PASID and PRI are only enumerated in PF devices.

2020-07-20 Thread Ashok Raj
PASID and PRI capabilities are only enumerated in PF devices. VF devices do not enumerate these capabilites. IOMMU drivers also need to enumerate them before enabling features in the IOMMU. Extending the same support as PASID feature discovery (pci_pasid_features) for PRI. Signed-off-by: Ashok

Re: [Freedreno] arm64: Internal error: Oops: qcom_iommu_tlb_inv_context free_io_pgtable_ops on db410c

2020-07-20 Thread Rob Clark
On Mon, Jul 20, 2020 at 4:28 AM Robin Murphy wrote: > > On 2020-07-20 08:17, Arnd Bergmann wrote: > > On Mon, Jul 20, 2020 at 8:36 AM Naresh Kamboju > > wrote: > >> > >> This kernel oops while boot linux mainline kernel on arm64 db410c device. > >> > >> metadata: > >>git branch: master > >>

[PATCH] iommu/qcom: Use domain rather than dev as tlb cookie

2020-07-20 Thread Rob Clark
From: Rob Clark The device may be torn down, but the domain should still be valid. Lets use that as the tlb flush ops cookie. Fixes a problem reported in [1] [1] https://lkml.org/lkml/2020/7/20/104 Signed-off-by: Rob Clark --- Note I don't have a good setup to test this atm, but I think it

Re: [PATCH v2 2/5] iommu/arm-smmu: Emulate bypass by using context banks

2020-07-20 Thread Jordan Crouse
On Mon, Jul 20, 2020 at 09:58:42AM +0100, Will Deacon wrote: > On Thu, Jul 16, 2020 at 05:16:16PM -0700, Bjorn Andersson wrote: > > Some firmware found on various Qualcomm platforms traps writes to S2CR > > of type BYPASS and writes FAULT into the register. This prevents us from > > marking the

[PATCH v10 08/13] drm/msm: Add a context pointer to the submitqueue

2020-07-20 Thread Jordan Crouse
Each submitqueue is attached to a context. Add a pointer to the context to the submitqueue at create time and refcount it so that it stays around through the life of the queue. GPU submissions can access the active context via the submitqueue instead of requiring it to be passed around from

[PATCH v10 12/13] drm/msm/a6xx: Add support for per-instance pagetables

2020-07-20 Thread Jordan Crouse
Add support for using per-instance pagetables if all the dependencies are available. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 +++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + 3 files

[PATCH v10 13/13] arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU

2020-07-20 Thread Jordan Crouse
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable split pagetables and per-instance pagetables for drm/msm. Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH v10 00/13] iommu/arm-smmu: Add Adreno SMMU specific implementation

2020-07-20 Thread Jordan Crouse
(reworded the summary to reflect ongoing changes in the code) This series adds an Adreno SMMU implementation to arm-smmu to allow GPU hardware pagetable switching. The Adreno GPU has built in capabilities to switch the TTBR0 pagetable during runtime to allow each individual instance or

[PATCH v10 01/13] iommu/arm-smmu: Pass io-pgtable config to implementation specific function

2020-07-20 Thread Jordan Crouse
Construct the io-pgtable config before calling the implementation specific init_context function and pass it so the implementation specific function can get a chance to change it before the io-pgtable is created. Signed-off-by: Jordan Crouse --- drivers/iommu/arm-smmu-impl.c | 3 ++-

[PATCH v10 03/13] iommu/arm-smmu: Add implementation hooks to configure contexts

2020-07-20 Thread Jordan Crouse
Add a new hook to allow implementations to implement their own context bank allocation scheme and update the existing init_context function to take the device pointer. These modifications will be used by the upcoming Adreno SMMU implementation to identify the GPU device and properly configure it

[PATCH v10 07/13] dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU

2020-07-20 Thread Jordan Crouse
Every Qcom Adreno GPU has an embedded SMMU for its own use. These devices depend on unique features such as split pagetables, different stall/halt requirements and other settings. Identify them with a compatible string so that they can be identified in the arm-smmu implementation specific code.

[PATCH v10 09/13] drm/msm: Set the global virtual address range from the IOMMU domain

2020-07-20 Thread Jordan Crouse
Use the aperture settings from the IOMMU domain to set up the virtual address range for the GPU. This allows us to transparently deal with IOMMU side features (like split pagetables). Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--

[PATCH v10 10/13] drm/msm: Add support to create a local pagetable

2020-07-20 Thread Jordan Crouse
Add support to create a io-pgtable for use by targets that support per-instance pagetables. In order to support per-instance pagetables the GPU SMMU device needs to have the qcom,adreno-smmu compatible string and split pagetables enabled. Signed-off-by: Jordan Crouse ---

[PATCH v10 02/13] iommu/arm-smmu: Add support for split pagetables

2020-07-20 Thread Jordan Crouse
Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected by the io-pgtable configuration. Signed-off-by: Jordan Crouse --- drivers/iommu/arm-smmu.c | 21 - drivers/iommu/arm-smmu.h | 25 +++-- 2 files changed, 35 insertions(+), 11

[PATCH v10 05/13] iommu: Add a domain attribute to get/set a pagetable configuration

2020-07-20 Thread Jordan Crouse
Add domain attribute DOMAIN_ATTR_PGTABLE_CFG. This will be used by arm-smmu to share the current pagetable configuration with the leaf driver and to allow the leaf driver to set up a new pagetable configuration under certain circumstances. Signed-off-by: Jordan Crouse --- include/linux/iommu.h

[PATCH v10 11/13] drm/msm: Add support for private address space instances

2020-07-20 Thread Jordan Crouse
Add support for allocating private address space instances. Targets that support per-context pagetables should implement their own function to allocate private address spaces. The default will return a pointer to the global address space. Signed-off-by: Jordan Crouse ---

[PATCH v10 04/13] iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU

2020-07-20 Thread Jordan Crouse
Add a special implementation for the SMMU attached to most Adreno GPU target triggered from the qcom,adreno-smmu compatible string. The new Adreno SMMU implementation will enable split pagetables (TTBR1) for the domain attached to the GPU device (SID 0) and hard code it context bank 0 so the GPU

[PATCH v10 06/13] iommu/arm-smmu-qcom: Get and set the pagetable config for split pagetables

2020-07-20 Thread Jordan Crouse
The Adreno GPU has the capability to manage its own pagetables and switch them dynamically from the hardware. To do this the GPU uses TTBR1 for "global" GPU memory and creates local pagetables for each context and switches them dynamically with the GPU. Use DOMAIN_ATTR_PGTABLE_CFG to get the

Re: [PATCH v8 00/12] iommu: Shared Virtual Addressing for SMMUv3 (PT sharing part)

2020-07-20 Thread Jean-Philippe Brucker
On Mon, Jul 20, 2020 at 12:11:17PM +0100, Will Deacon wrote: > On Thu, Jun 18, 2020 at 05:51:13PM +0200, Jean-Philippe Brucker wrote: > > Since v7 [1], I split the series into three parts to ease review. This > > first one adds page table sharing to the SMMUv3 driver. The second one > > adds

RE: [PATCH v5 15/15] iommu/vt-d: Support reporting nesting capability info

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Saturday, July 18, 2020 1:14 AM > > Hi Yi, > > Missing a proper commit message. You can comment on the fact you only > support the case where all the physical iomms have the same CAP/ECAP MASKS got it. will add it. it looks like the subject is

RE: [PATCH v5 13/15] vfio/pci: Expose PCIe PASID capability to guest

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Monday, July 20, 2020 8:35 PM > > Yi, > > On 7/12/20 1:21 PM, Liu Yi L wrote: > > This patch exposes PCIe PASID capability to guest for assigned devices. > > Existing vfio_pci driver hides it from guest by setting the capability > > length as 0 in

RE: [PATCH v5 09/15] iommu/vt-d: Check ownership for PASIDs from user-space

2020-07-20 Thread Liu, Yi L
Eric, > From: Auger Eric > Sent: Monday, July 20, 2020 8:38 PM > > Yi, > > On 7/20/20 12:18 PM, Liu, Yi L wrote: > > Hi Eric, > > > >> From: Auger Eric > >> Sent: Monday, July 20, 2020 12:06 AM > >> > >> Hi Yi, > >> > >> On 7/12/20 1:21 PM, Liu Yi L wrote: > >>> When an IOMMU domain with

Re: [PATCH v5 09/15] iommu/vt-d: Check ownership for PASIDs from user-space

2020-07-20 Thread Auger Eric
Yi, On 7/20/20 12:18 PM, Liu, Yi L wrote: > Hi Eric, > >> From: Auger Eric >> Sent: Monday, July 20, 2020 12:06 AM >> >> Hi Yi, >> >> On 7/12/20 1:21 PM, Liu Yi L wrote: >>> When an IOMMU domain with nesting attribute is used for guest SVA, a >>> system-wide PASID is allocated for binding with

Re: [PATCH v5 13/15] vfio/pci: Expose PCIe PASID capability to guest

2020-07-20 Thread Auger Eric
Yi, On 7/12/20 1:21 PM, Liu Yi L wrote: > This patch exposes PCIe PASID capability to guest for assigned devices. > Existing vfio_pci driver hides it from guest by setting the capability > length as 0 in pci_ext_cap_length[]. > > And this patch only exposes PASID capability for devices which has

Re: [PATCH v5 12/15] vfio/type1: Add vSVA support for IOMMU-backed mdevs

2020-07-20 Thread Auger Eric
Yi, On 7/12/20 1:21 PM, Liu Yi L wrote: > Recent years, mediated device pass-through framework (e.g. vfio-mdev) > is used to achieve flexible device sharing across domains (e.g. VMs). > Also there are hardware assisted mediated pass-through solutions from > platform vendors. e.g. Intel VT-d

Re: [PATCH v11 0/5] NVIDIA ARM SMMU Implementation

2020-07-20 Thread Will Deacon
On Sat, 18 Jul 2020 12:34:52 -0700, Krishna Reddy wrote: > Changes in v11: > Addressed Rob comment on DT binding patch to set min/maxItems of reg property > in else part. > Rebased on top of > https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/updates. > >

Re: arm64: Internal error: Oops: qcom_iommu_tlb_inv_context free_io_pgtable_ops on db410c

2020-07-20 Thread Robin Murphy
On 2020-07-20 08:17, Arnd Bergmann wrote: On Mon, Jul 20, 2020 at 8:36 AM Naresh Kamboju wrote: This kernel oops while boot linux mainline kernel on arm64 db410c device. metadata: git branch: master git repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git git

Re: [PATCH v8 00/12] iommu: Shared Virtual Addressing for SMMUv3 (PT sharing part)

2020-07-20 Thread Will Deacon
On Thu, Jun 18, 2020 at 05:51:13PM +0200, Jean-Philippe Brucker wrote: > Since v7 [1], I split the series into three parts to ease review. This > first one adds page table sharing to the SMMUv3 driver. The second one > adds support for I/O page faults through PRI and Stall, and the last one > adds

RE: [PATCH v5 11/15] vfio/type1: Allow invalidating first-level/stage IOMMU cache

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Monday, July 20, 2020 5:42 PM > > Yi, > > On 7/12/20 1:21 PM, Liu Yi L wrote: > > This patch provides an interface allowing the userspace to invalidate > > IOMMU cache for first-level page table. It is required when the first > > level IOMMU page table is

RE: [PATCH v5 10/15] vfio/type1: Support binding guest page tables to PASID

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Monday, July 20, 2020 5:37 PM > > Yi, > > On 7/12/20 1:21 PM, Liu Yi L wrote: > > Nesting translation allows two-levels/stages page tables, with 1st level > > for guest translations (e.g. GVA->GPA), 2nd level for host translations > > (e.g. GPA->HPA). This

RE: [PATCH v5 09/15] iommu/vt-d: Check ownership for PASIDs from user-space

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Monday, July 20, 2020 12:06 AM > > Hi Yi, > > On 7/12/20 1:21 PM, Liu Yi L wrote: > > When an IOMMU domain with nesting attribute is used for guest SVA, a > > system-wide PASID is allocated for binding with the device and the domain. > > For security reason,

Re: [PATCH v5 11/15] vfio/type1: Allow invalidating first-level/stage IOMMU cache

2020-07-20 Thread Auger Eric
Yi, On 7/12/20 1:21 PM, Liu Yi L wrote: > This patch provides an interface allowing the userspace to invalidate > IOMMU cache for first-level page table. It is required when the first > level IOMMU page table is not managed by the host kernel in the nested > translation setup. > > Cc: Kevin Tian

Re: [PATCH v5 10/15] vfio/type1: Support binding guest page tables to PASID

2020-07-20 Thread Auger Eric
Yi, On 7/12/20 1:21 PM, Liu Yi L wrote: > Nesting translation allows two-levels/stages page tables, with 1st level > for guest translations (e.g. GVA->GPA), 2nd level for host translations > (e.g. GPA->HPA). This patch adds interface for binding guest page tables > to a PASID. This PASID must

RE: [PATCH v5 08/15] iommu: Pass domain to sva_unbind_gpasid()

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Sunday, July 19, 2020 11:38 PM > > Yi, > > On 7/12/20 1:21 PM, Liu Yi L wrote: > > From: Yi Sun > > > > Current interface is good enough for SVA virtualization on an assigned > > physical PCI device, but when it comes to mediated devices, a physical > >

Re: [PATCH v2 5/5] iommu/arm-smmu: Setup identity domain for boot mappings

2020-07-20 Thread Will Deacon
On Thu, Jul 16, 2020 at 05:16:19PM -0700, Bjorn Andersson wrote: > With many Qualcomm platforms not having functional S2CR BYPASS a > temporary IOMMU domain, without translation, needs to be allocated in > order to allow these memory transactions. > > Unfortunately the boot loader uses the first

Re: [PATCH v2 2/5] iommu/arm-smmu: Emulate bypass by using context banks

2020-07-20 Thread Will Deacon
On Thu, Jul 16, 2020 at 05:16:16PM -0700, Bjorn Andersson wrote: > Some firmware found on various Qualcomm platforms traps writes to S2CR > of type BYPASS and writes FAULT into the register. This prevents us from > marking the streams for the display controller as BYPASS to allow > continued

RE: [PATCH v5 07/15] vfio/type1: Add VFIO_IOMMU_PASID_REQUEST (alloc/free)

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Sunday, July 19, 2020 11:39 PM > > Yi, > > On 7/12/20 1:21 PM, Liu Yi L wrote: > > This patch allows user space to request PASID allocation/free, e.g. > > when serving the request from the guest. > > > > PASIDs that are not freed by userspace are

RE: [PATCH v5 04/15] vfio/type1: Report iommu nesting info to userspace

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Monday, July 20, 2020 4:33 PM > > Yi, > > On 7/20/20 9:51 AM, Liu, Yi L wrote: > > Hi Eric, > > > >> From: Auger Eric > >> Sent: Saturday, July 18, 2020 1:34 AM > >> > >> Yi, > >> > >> On 7/12/20 1:20 PM, Liu Yi L wrote: > >>> This patch exports iommu

RE: [PATCH v5 05/15] vfio: Add PASID allocation/free support

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Monday, July 20, 2020 4:26 PM [...] > >>> +int vfio_pasid_alloc(struct vfio_mm *vmm, int min, int max) { > >>> + ioasid_t pasid; > >>> + struct vfio_pasid *vid; > >>> + > >>> + pasid = ioasid_alloc(vmm->ioasid_sid, min, max, NULL); > >>> + if (pasid ==

Re: [PATCH v5 04/15] vfio/type1: Report iommu nesting info to userspace

2020-07-20 Thread Auger Eric
Yi, On 7/20/20 9:51 AM, Liu, Yi L wrote: > Hi Eric, > >> From: Auger Eric >> Sent: Saturday, July 18, 2020 1:34 AM >> >> Yi, >> >> On 7/12/20 1:20 PM, Liu Yi L wrote: >>> This patch exports iommu nesting capability info to user space through >>> VFIO. User space is expected to check this info

Re: [PATCH v5 05/15] vfio: Add PASID allocation/free support

2020-07-20 Thread Auger Eric
Hi Yi, On 7/20/20 10:03 AM, Liu, Yi L wrote: > Hi Eric, > >> From: Auger Eric >> Sent: Sunday, July 19, 2020 11:39 PM >> >> Yi, >> >> On 7/12/20 1:21 PM, Liu Yi L wrote: >>> Shared Virtual Addressing (a.k.a Shared Virtual Memory) allows sharing >>> multiple process virtual address spaces with

RE: [PATCH v5 06/15] iommu/vt-d: Support setting ioasid set to domain

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Sunday, July 19, 2020 11:38 PM > > Yi, > > On 7/12/20 1:21 PM, Liu Yi L wrote: > > From IOMMU p.o.v., PASIDs allocated and managed by external components > > (e.g. VFIO) will be passed in for gpasid_bind/unbind operation. IOMMU > > needs some knowledge to

RE: [PATCH v5 05/15] vfio: Add PASID allocation/free support

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Sunday, July 19, 2020 11:39 PM > > Yi, > > On 7/12/20 1:21 PM, Liu Yi L wrote: > > Shared Virtual Addressing (a.k.a Shared Virtual Memory) allows sharing > > multiple process virtual address spaces with the device for simplified > > programming model. PASID

RE: [PATCH v5 04/15] vfio/type1: Report iommu nesting info to userspace

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Saturday, July 18, 2020 1:34 AM > > Yi, > > On 7/12/20 1:20 PM, Liu Yi L wrote: > > This patch exports iommu nesting capability info to user space through > > VFIO. User space is expected to check this info for supported uAPIs (e.g. > it is not only to check

RE: [PATCH v5 03/15] iommu/smmu: Report empty domain nesting info

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > > Yi, > > On 7/12/20 1:20 PM, Liu Yi L wrote: > > This patch is added as instead of returning a boolean for > > DOMAIN_ATTR_NESTING, > > iommu_domain_get_attr() should return an iommu_nesting_info handle. > > you may add in the commit message you return an empty

RE: [PATCH v5 02/15] iommu: Report domain nesting info

2020-07-20 Thread Liu, Yi L
Hi Eric, > From: Auger Eric > Sent: Saturday, July 18, 2020 12:29 AM > > Hi Yi, > > On 7/12/20 1:20 PM, Liu Yi L wrote: > > IOMMUs that support nesting translation needs report the capability info > s/needs/need to report yep. > > to userspace, e.g. the format of first level/stage paging

Re: arm64: Internal error: Oops: qcom_iommu_tlb_inv_context free_io_pgtable_ops on db410c

2020-07-20 Thread Arnd Bergmann
On Mon, Jul 20, 2020 at 8:36 AM Naresh Kamboju wrote: > > This kernel oops while boot linux mainline kernel on arm64 db410c device. > > metadata: > git branch: master > git repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git > git commit:

arm64: Internal error: Oops: qcom_iommu_tlb_inv_context free_io_pgtable_ops on db410c

2020-07-20 Thread Naresh Kamboju
This kernel oops while boot linux mainline kernel on arm64 db410c device. metadata: git branch: master git repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git git commit: f8456690ba8eb18ea4714e68554e242a04f65cff git describe: v5.8-rc5-48-gf8456690ba8e

Re: [PATCH] dma-debug: use named initializers for dir2name

2020-07-20 Thread Christoph Hellwig
On Thu, Jul 16, 2020 at 05:12:30PM +0100, Robin Murphy wrote: >> +static const char *dir2name[4] = { > > Nit: I think you can probably drop the explicit array size here. > > Otherwise, very welcome clarity! > > Reviewed-by: Robin Murphy Applied with the explicit array size removed.

Re: [PATCH 3/5] dma-mapping: make support for dma ops optional

2020-07-20 Thread Christoph Hellwig
On Sat, Jul 18, 2020 at 10:17:14AM -0700, Guenter Roeck wrote: > On Wed, Jul 08, 2020 at 05:24:47PM +0200, Christoph Hellwig wrote: > > Avoid the overhead of the dma ops support for tiny builds that only > > use the direct mapping. > > > > Signed-off-by: Christoph Hellwig > > For