[PATCH] iommu: fix return error code in iommu_probe_device()

2020-11-16 Thread Yang Yingliang
If iommu_group_get() failed, it need return error code in iommu_probe_device(). Fixes: cf193888bfbd ("iommu: Move new probe_device path...") Reported-by: Hulk Robot Signed-off-by: Yang Yingliang --- drivers/iommu/iommu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/dri

Re: [PATCH v11 01/13] vfio: VFIO_IOMMU_SET_PASID_TABLE

2020-11-16 Thread kernel test robot
Hi Eric, Thank you for the patch! Yet something to improve: [auto build test ERROR on v5.10-rc4] [also build test ERROR on next-20201116] [cannot apply to vfio/next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--bas

Re: iommu/vt-d: Cure VF irqdomain hickup

2020-11-16 Thread Jason Gunthorpe
On Thu, Nov 12, 2020 at 08:15:02PM +0100, Thomas Gleixner wrote: > The recent changes to store the MSI irqdomain pointer in struct device > missed that Intel DMAR does not register virtual function devices. Due to > that a VF device gets the plain PCI-MSI domain assigned and then issues > compat M

Re: [PATCH v6 3/3] firmware: QCOM_SCM: Allow qcom_scm driver to be loadable as a permenent module

2020-11-16 Thread John Stultz
On Mon, Nov 16, 2020 at 8:36 AM Will Deacon wrote: > On Mon, Nov 16, 2020 at 04:59:36PM +0100, Thierry Reding wrote: > > On Fri, Nov 06, 2020 at 04:27:10AM +, John Stultz wrote: > > Unfortunately, the ARM SMMU module will eventually end up being loaded > > once the root filesystem has been mou

Re: [PATCH 1/1] vfio/type1: Add subdev_ioasid callback to vfio_iommu_driver_ops

2020-11-16 Thread Alex Williamson
On Thu, 12 Nov 2020 10:24:07 +0800 Lu Baolu wrote: > Add API for getting the ioasid of a subdevice (vfio/mdev). This calls > into the backend IOMMU module to get the actual value or error number > if ioasid for subdevice is not supported. The physical device driver > implementations which rely on

Re: [PATCH v6 3/3] firmware: QCOM_SCM: Allow qcom_scm driver to be loadable as a permenent module

2020-11-16 Thread John Stultz
On Mon, Nov 16, 2020 at 7:59 AM Thierry Reding wrote: > > On Fri, Nov 06, 2020 at 04:27:10AM +, John Stultz wrote: > > diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig > > index 04878caf6da49..c64d7a2b65134 100644 > > --- a/drivers/iommu/Kconfig > > +++ b/drivers/iommu/Kconfig > > @@

Re: [PATCH v11 05/13] vfio/pci: Register an iommu fault handler

2020-11-16 Thread kernel test robot
Hi Eric, I love your patch! Perhaps something to improve: [auto build test WARNING on v5.10-rc4] [also build test WARNING on next-20201116] [cannot apply to vfio/next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--bas

Re: [PATCH v4 04/24] dt-bindings: memory: mediatek: Add domain definition

2020-11-16 Thread Rob Herring
On Wed, 11 Nov 2020 20:38:18 +0800, Yong Wu wrote: > In the latest SoC, there are several HW IP require a sepecial iova > range, mainly CCU and VPU has this requirement. Take CCU as a example, > CCU require its iova locate in the range(0x4000_ ~ 0x43ff_). > > In this patch we add a domain

Re: [PATCH v4 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema

2020-11-16 Thread Rob Herring
On Wed, 11 Nov 2020 20:38:15 +0800, Yong Wu wrote: > Convert MediaTek IOMMU to DT schema. > > Signed-off-by: Yong Wu > --- > .../bindings/iommu/mediatek,iommu.txt | 105 --- > .../bindings/iommu/mediatek,iommu.yaml| 167 ++ > 2 files changed, 167 insertion

Re: [PATCH v6 3/3] firmware: QCOM_SCM: Allow qcom_scm driver to be loadable as a permenent module

2020-11-16 Thread Will Deacon
On Mon, Nov 16, 2020 at 04:59:36PM +0100, Thierry Reding wrote: > On Fri, Nov 06, 2020 at 04:27:10AM +, John Stultz wrote: > > diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c > > index 7be48c1bec96d..6f431b73e617d 100644 > > --- a/drivers/firmware/qcom_scm.c > > +++ b/dri

Re: [PATCH v12 15/15] iommu/smmuv3: Add PASID cache invalidation per PASID

2020-11-16 Thread kernel test robot
Hi Eric, I love your patch! Perhaps something to improve: [auto build test WARNING on iommu/next] [also build test WARNING on linus/master v5.10-rc4 next-20201116] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--bas

Re: [PATCH v6 3/3] firmware: QCOM_SCM: Allow qcom_scm driver to be loadable as a permenent module

2020-11-16 Thread Thierry Reding
On Fri, Nov 06, 2020 at 04:27:10AM +, John Stultz wrote: > Allow the qcom_scm driver to be loadable as a permenent module. > > This still uses the "depends on QCOM_SCM || !QCOM_SCM" bit to > ensure that drivers that call into the qcom_scm driver are > also built as modules. While not ideal in

Re: [PATCH v12 01/15] iommu: Introduce attach/detach_pasid_table API

2020-11-16 Thread kernel test robot
Hi Eric, I love your patch! Perhaps something to improve: [auto build test WARNING on iommu/next] [also build test WARNING on linus/master v5.10-rc4 next-20201116] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--bas

Re: [PATCH v11 05/13] vfio/pci: Register an iommu fault handler

2020-11-16 Thread kernel test robot
Hi Eric, I love your patch! Perhaps something to improve: [auto build test WARNING on v5.10-rc4] [also build test WARNING on next-20201116] [cannot apply to vfio/next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--bas

Re: iommu/vt-d: Cure VF irqdomain hickup

2020-11-16 Thread Lu Baolu
On 2020/11/16 17:47, Geert Uytterhoeven wrote: Hi Thomas, On Thu, Nov 12, 2020 at 8:16 PM Thomas Gleixner wrote: The recent changes to store the MSI irqdomain pointer in struct device missed that Intel DMAR does not register virtual function devices. Due to that a VF device gets the plain PCI

Re: iommu/vt-d: Cure VF irqdomain hickup

2020-11-16 Thread Thomas Gleixner
Geert, On Mon, Nov 16 2020 at 10:47, Geert Uytterhoeven wrote: > On Thu, Nov 12, 2020 at 8:16 PM Thomas Gleixner wrote: >> The recent changes to store the MSI irqdomain pointer in struct device >> missed that Intel DMAR does not register virtual function devices. Due to >> that a VF device gets

[PATCH v11 13/13] vfio/pci: Inject page response upon response region fill

2020-11-16 Thread Eric Auger
When the userspace increments the head of the page response buffer ring, let's push the response into the iommu layer. This is done through a workqueue that pops the responses from the ring buffer and increment the tail. Signed-off-by: Eric Auger --- drivers/vfio/pci/vfio_pci.c | 40

[PATCH v11 12/13] vfio/pci: Register a DMA fault response region

2020-11-16 Thread Eric Auger
In preparation for vSVA, let's register a DMA fault response region, where the userspace will push the page responses and increment the head of the buffer. The kernel will pop those responses and inject them on iommu side. Signed-off-by: Eric Auger --- drivers/vfio/pci/vfio_pci.c | 114 +

[PATCH v11 11/13] vfio: Document nested stage control

2020-11-16 Thread Eric Auger
The VFIO API was enhanced to support nested stage control: a bunch of new iotcls, one DMA FAULT region and an associated specific IRQ. Let's document the process to follow to set up nested mode. Signed-off-by: Eric Auger --- v11 -> v12: s/VFIO_REGION_INFO_CAP_PRODUCER_FAULT/VFIO_REGION_INFO_CA

[PATCH v11 07/13] vfio: Use capability chains to handle device specific irq

2020-11-16 Thread Eric Auger
From: Tina Zhang Caps the number of irqs with fixed indexes and uses capability chains to chain device specific irqs. Signed-off-by: Tina Zhang Signed-off-by: Eric Auger [Eric: Put cap_offset at the end of the vfio_irq_info struct, remove GFX IRQ at the moment and remove any reference to this

[PATCH v11 05/13] vfio/pci: Register an iommu fault handler

2020-11-16 Thread Eric Auger
Register an IOMMU fault handler which records faults in the DMA FAULT region ring buffer. In a subsequent patch, we will add the signaling of a specific eventfd to allow the userspace to be notified whenever a new fault as shown up. Signed-off-by: Eric Auger --- v11 -> v12: - take the fault_queu

[PATCH v11 09/13] vfio: Add new IRQ for DMA fault reporting

2020-11-16 Thread Eric Auger
Add a new IRQ type/subtype to get notification on nested stage DMA faults. Signed-off-by: Eric Auger --- include/uapi/linux/vfio.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 0e2bfbeccd08..1e5c82f9d14d 100644 --- a/include/ua

[PATCH v11 03/13] vfio: VFIO_IOMMU_SET_MSI_BINDING

2020-11-16 Thread Eric Auger
This patch adds the VFIO_IOMMU_SET_MSI_BINDING ioctl which aim to (un)register the guest MSI binding to the host. This latter then can use those stage 1 bindings to build a nested stage binding targeting the physical MSIs. Signed-off-by: Eric Auger --- v10 -> v11: - renamed ustruct into msi_bin

[PATCH v11 04/13] vfio/pci: Add VFIO_REGION_TYPE_NESTED region type

2020-11-16 Thread Eric Auger
Add a new specific DMA_FAULT region aiming to exposed nested mode translation faults. This region only is exposed if the device is attached to a nested domain. The region has a ring buffer that contains the actual fault records plus a header allowing to handle it (tail/head indices, max capacity,

[PATCH v11 10/13] vfio/pci: Register and allow DMA FAULT IRQ signaling

2020-11-16 Thread Eric Auger
Register the VFIO_IRQ_TYPE_NESTED/VFIO_IRQ_SUBTYPE_DMA_FAULT IRQ that allows to signal a nested mode DMA fault. Signed-off-by: Eric Auger --- v10 -> v11: - the irq now is registered in vfio_pci_dma_fault_init() in case the domain is nested --- drivers/vfio/pci/vfio_pci.c | 21 +++

[PATCH v11 08/13] vfio/pci: Add framework for custom interrupt indices

2020-11-16 Thread Eric Auger
Implement IRQ capability chain infrastructure. All interrupt indexes beyond VFIO_PCI_NUM_IRQS are handled as extended interrupts. They are registered with a specific type/subtype and supported flags. Signed-off-by: Eric Auger --- drivers/vfio/pci/vfio_pci.c | 99 +++--

[PATCH v11 06/13] vfio/pci: Allow to mmap the fault queue

2020-11-16 Thread Eric Auger
The DMA FAULT region contains the fault ring buffer. There is benefit to let the userspace mmap this area. Expose this mmappable area through a sparse mmap entry and implement the mmap operation. Signed-off-by: Eric Auger --- v8 -> v9: - remove unused index local variable in vfio_pci_fault_mmap

[PATCH v11 01/13] vfio: VFIO_IOMMU_SET_PASID_TABLE

2020-11-16 Thread Eric Auger
From: "Liu, Yi L" This patch adds an VFIO_IOMMU_SET_PASID_TABLE ioctl which aims to pass the virtual iommu guest configuration to the host. This latter takes the form of the so-called PASID table. Signed-off-by: Jacob Pan Signed-off-by: Liu, Yi L Signed-off-by: Eric Auger --- v11 -> v12: - u

[PATCH v11 02/13] vfio: VFIO_IOMMU_CACHE_INVALIDATE

2020-11-16 Thread Eric Auger
From: "Liu, Yi L" When the guest "owns" the stage 1 translation structures, the host IOMMU driver has no knowledge of caching structure updates unless the guest invalidation requests are trapped and passed down to the host. This patch adds the VFIO_IOMMU_CACHE_INVALIDATE ioctl with aims at prop

[PATCH v11 00/13] SMMUv3 Nested Stage Setup (VFIO part)

2020-11-16 Thread Eric Auger
This series brings the VFIO part of HW nested paging support in the SMMUv3. This is a rebase on top of v5.10-rc4 The series depends on: [PATCH v12 00/15] SMMUv3 Nested Stage Setup (IOMMU part) 3 new IOCTLs are introduced that allow the userspace to 1) pass the guest stage 1 configuration 2) pass

[PATCH v12 15/15] iommu/smmuv3: Add PASID cache invalidation per PASID

2020-11-16 Thread Eric Auger
In order to cascade guest CFGI_CD, let's add PASID cache invalidation per PASID. Signed-off-by: Eric Auger --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/

[PATCH v12 12/15] iommu/smmuv3: Implement bind/unbind_guest_msi

2020-11-16 Thread Eric Auger
The bind/unbind_guest_msi() callbacks check the domain is NESTED and redirect to the dma-iommu implementation. Signed-off-by: Eric Auger --- v6 -> v7: - remove device handle argument --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 43 + 1 file changed, 43 insertions(+) d

[PATCH v12 13/15] iommu/smmuv3: Report non recoverable faults

2020-11-16 Thread Eric Auger
When a stage 1 related fault event is read from the event queue, let's propagate it to potential external fault listeners, ie. users who registered a fault handler. Signed-off-by: Eric Auger --- v8 -> v9: - adapt to the removal of IOMMU_FAULT_UNRECOV_PERM_VALID: only look at IOMMU_FAULT_UNRECO

[PATCH v12 08/15] iommu/smmuv3: Implement cache_invalidate

2020-11-16 Thread Eric Auger
Implement domain-selective and page-selective IOTLB invalidations. Signed-off-by: Eric Auger --- v7 -> v8: - ASID based invalidation using iommu_inv_pasid_info - check ARCHID/PASID flags in addr based invalidation - use __arm_smmu_tlb_inv_context and __arm_smmu_tlb_inv_range_nosync v6 -> v7 - c

[PATCH v12 09/15] dma-iommu: Implement NESTED_MSI cookie

2020-11-16 Thread Eric Auger
Up to now, when the type was UNMANAGED, we used to allocate IOVA pages within a reserved IOVA MSI range. If both the host and the guest are exposed with SMMUs, each would allocate an IOVA. The guest allocates an IOVA (gIOVA) to map onto the guest MSI doorbell (gDB). The Host allocates another IOVA

[PATCH v12 07/15] iommu/smmuv3: Allow stage 1 invalidation with unmanaged ASIDs

2020-11-16 Thread Eric Auger
With nested stage support, soon we will need to invalidate S1 contexts and ranges tagged with an unmanaged asid, this latter being managed by the guest. So let's introduce 2 helpers that allow to invalidate with externally managed ASIDs Signed-off-by: Eric Auger --- drivers/iommu/arm/arm-smmu-v3

[PATCH v12 14/15] iommu/smmuv3: Accept configs with more than one context descriptor

2020-11-16 Thread Eric Auger
In preparation for vSVA, let's accept userspace provided configs with more than one CD. We check the max CD against the host iommu capability and also the format (linear versus 2 level). Signed-off-by: Eric Auger Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c |

[PATCH v12 10/15] iommu/smmuv3: Nested mode single MSI doorbell per domain enforcement

2020-11-16 Thread Eric Auger
In nested mode we enforce the rule that all devices belonging to the same iommu_domain share the same msi_domain. Indeed if there were several physical MSI doorbells being used within a single iommu_domain, it becomes really difficult to resolve the nested stage mapping translating into the correc

[PATCH v12 11/15] iommu/smmuv3: Enforce incompatibility between nested mode and HW MSI regions

2020-11-16 Thread Eric Auger
Nested mode currently is not compatible with HW MSI reserved regions. Indeed MSI transactions targeting this MSI doorbells bypass the SMMU. Let's check nested mode is not attempted in such configuration. Signed-off-by: Eric Auger --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 23

[PATCH v12 05/15] iommu/smmuv3: Get prepared for nested stage support

2020-11-16 Thread Eric Auger
When nested stage translation is setup, both s1_cfg and s2_cfg are allocated. We introduce a new smmu domain abort field that will be set upon guest stage1 configuration passing. arm_smmu_write_strtab_ent() is modified to write both stage fields in the STE and deal with the abort field. In neste

[PATCH v12 00/15] SMMUv3 Nested Stage Setup (IOMMU part)

2020-11-16 Thread Eric Auger
This series brings the IOMMU part of HW nested paging support in the SMMUv3. The VFIO part is submitted separately. The IOMMU API is extended to support 2 new API functionalities: 1) pass the guest stage 1 configuration 2) pass stage 1 MSI bindings Then those capabilities gets implemented in the

[PATCH v12 06/15] iommu/smmuv3: Implement attach/detach_pasid_table

2020-11-16 Thread Eric Auger
On attach_pasid_table() we program STE S1 related info set by the guest into the actual physical STEs. At minimum we need to program the context descriptor GPA and compute whether the stage1 is translated/bypassed or aborted. Signed-off-by: Eric Auger --- v7 -> v8: - remove smmu->features check,

[PATCH v12 03/15] iommu/arm-smmu-v3: Maintain a SID->device structure

2020-11-16 Thread Eric Auger
When handling faults from the event or PRI queue, we need to find the struct device associated to a SID. Add a rb_tree to keep track of SIDs. Signed-off-by: Eric Auger Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 99 + drivers/iommu/

[PATCH v12 02/15] iommu: Introduce bind/unbind_guest_msi

2020-11-16 Thread Eric Auger
On ARM, MSI are translated by the SMMU. An IOVA is allocated for each MSI doorbell. If both the host and the guest are exposed with SMMUs, we end up with 2 different IOVAs allocated by each. guest allocates an IOVA (gIOVA) to map onto the guest MSI doorbell (gDB). The Host allocates another IOVA (h

[PATCH v12 01/15] iommu: Introduce attach/detach_pasid_table API

2020-11-16 Thread Eric Auger
In virtualization use case, when a guest is assigned a PCI host device, protected by a virtual IOMMU on the guest, the physical IOMMU must be programmed to be consistent with the guest mappings. If the physical IOMMU supports two translation stages it makes sense to program guest mappings onto the

[PATCH v12 04/15] iommu/smmuv3: Dynamically allocate s1_cfg and s2_cfg

2020-11-16 Thread Eric Auger
In preparation for the introduction of nested stages let's turn s1_cfg and s2_cfg fields into pointers which are dynamically allocated depending on the smmu_domain stage. In nested mode, both stages will coexist and s1_cfg will be allocated when the guest configuration gets passed. Signed-off-by:

Re: iommu/vt-d: Cure VF irqdomain hickup

2020-11-16 Thread Geert Uytterhoeven
Hi Thomas, On Thu, Nov 12, 2020 at 8:16 PM Thomas Gleixner wrote: > The recent changes to store the MSI irqdomain pointer in struct device > missed that Intel DMAR does not register virtual function devices. Due to > that a VF device gets the plain PCI-MSI domain assigned and then issues > compa