Re: [PATCH v5] swiotlb: Adjust SWIOTBL bounce buffer size for SEV guests.

2020-11-18 Thread Christoph Hellwig
On Wed, Nov 18, 2020 at 08:12:43PM +, Ashish Kalra wrote: > From: Ashish Kalra > > For SEV, all DMA to and from guest has to use shared > (un-encrypted) pages. SEV uses SWIOTLB to make this > happen without requiring changes to device drivers. > However, depending on workload being run, the

[PATCH v2 6/6] iommu/mediatek: Convert tlb_flush_walk to gather_add_page

2020-11-18 Thread Yong Wu
MediaTek TLB flush don't care about granule. when unmap, it could gather whole the iova range then do tlb flush once. In current v7s, If unmap the lvl2 pagetable, the steps are: step1: set this current pdg to 0. step2: tlb flush for this lvl2 block iova(1M). step3: free the lvl2 pagetable. This

[PATCH v2 5/6] iommu/mediatek: Enable granule_ignore for unmap

2020-11-18 Thread Yong Wu
MediaTek IOMMU HW don't care about granule when it flush tlb. In order to flush tlb once when unmap, Enable this flag to gather all the iova chunk of unmap. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/mtk_iommu.c

[PATCH v2 4/6] iommu: Add granule_ignore when tlb gather

2020-11-18 Thread Yong Wu
Add a granule_ignore option when tlb gather for some HW which don't care about granule when it flush tlb. Signed-off-by: Yong Wu --- include/linux/iommu.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index

[PATCH v2 3/6] iommu/mediatek: Add iotlb_sync_map to sync whole the iova range

2020-11-18 Thread Yong Wu
Remove IO_PGTABLE_QUIRK_TLBI_ON_MAP to avoid tlb sync for each a small chunk memory, Use the new iotlb_sync_map to tlb_sync once for whole the iova range of iommu_map. Signed-off-by: Yong Wu --- After reading msm_iommu.c, It looks IO_PGTABLE_QUIRK_TLBI_ON_MAP can be removed. ---

[PATCH v2 2/6] iommu: Add iova and size as parameters in iommu_iotlb_map

2020-11-18 Thread Yong Wu
iotlb_sync_map allow IOMMU drivers tlb sync after completing the whole mapping. This patch adds iova and size as the parameters in it. then the IOMMU driver could flush tlb with the whole range once after iova mapping to improve performance. Signed-off-by: Yong Wu --- drivers/iommu/iommu.c

[PATCH v2 1/6] iommu: Move iotlb_sync_map out from __iommu_map

2020-11-18 Thread Yong Wu
In the end of __iommu_map, It alway call iotlb_sync_map. This patch moves iotlb_sync_map out from __iommu_map since it is unnecessary to call this for each sg segment especially iotlb_sync_map is flush tlb all currently. Signed-off-by: Yong Wu --- drivers/iommu/iommu.c | 24

[PATCH v2 0/6] MediaTek IOMMU improve tlb flush performance in map/unmap

2020-11-18 Thread Yong Wu
This patchset is to improve tlb flushing performance in iommu_map/unmap for MediaTek IOMMU. For iommu_map, currently MediaTek IOMMU use IO_PGTABLE_QUIRK_TLBI_ON_MAP to do tlb_flush for each a memory chunk. this is so unnecessary. we could improve it by tlb flushing one time at the end of

[PATCH 1/1] iommu/vt-d: Fix compile error with CONFIG_PCI_ATS not set

2020-11-18 Thread Lu Baolu
Fix the compile error below (CONFIG_PCI_ATS not set): drivers/iommu/intel/dmar.c: In function ‘vf_inherit_msi_domain’: drivers/iommu/intel/dmar.c:338:59: error: ‘struct pci_dev’ has no member named ‘physfn’; did you mean ‘is_physfn’? 338 | dev_set_msi_domain(>dev,

Re: [PATCH v13 05/15] iommu/smmuv3: Get prepared for nested stage support

2020-11-18 Thread kernel test robot
Hi Eric, I love your patch! Perhaps something to improve: [auto build test WARNING on iommu/next] [also build test WARNING on linus/master v5.10-rc4 next-20201118] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base

Re: [Patch V8 0/3] iommu: Add support to change default domain of an iommu group

2020-11-18 Thread Lu Baolu
On 11/18/20 9:52 PM, Will Deacon wrote: On Fri, Sep 25, 2020 at 12:06:17PM -0700, Ashok Raj wrote: Presently, the default domain of an iommu group is allocated during boot time and it cannot be changed later. So, the device would typically be either in identity (pass_through) mode or the device

Re: [Patch V8 3/3] iommu: Document usage of "/sys/kernel/iommu_groups//type" file

2020-11-18 Thread Lu Baolu
Hi Will, On 11/18/20 9:51 PM, Will Deacon wrote: On Fri, Sep 25, 2020 at 12:06:20PM -0700, Ashok Raj wrote: From: Sai Praneeth Prakhya The default domain type of an iommu group can be changed by writing to "/sys/kernel/iommu_groups//type" file. Hence, document it's usage and more importantly

Re: [Patch V8 1/3] iommu: Add support to change default domain of an iommu group

2020-11-18 Thread Lu Baolu
Hi Will, The original author of this patch series has left Intel. I am now the backup. On 11/18/20 9:51 PM, Will Deacon wrote: On Fri, Sep 25, 2020 at 12:06:18PM -0700, Ashok Raj wrote: From: Sai Praneeth Prakhya Presently, the default domain of an iommu group is allocated during boot time

Re: [PATCH v5] swiotlb: Adjust SWIOTBL bounce buffer size for SEV guests.

2020-11-18 Thread Borislav Petkov
On Wed, Nov 18, 2020 at 08:12:43PM +, Ashish Kalra wrote: > diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c > index 3511736fbc74..0f42911cea57 100644 > --- a/arch/x86/kernel/setup.c > +++ b/arch/x86/kernel/setup.c > @@ -1166,6 +1166,10 @@ void __init setup_arch(char **cmdline_p)

[PATCH v5] swiotlb: Adjust SWIOTBL bounce buffer size for SEV guests.

2020-11-18 Thread Ashish Kalra
From: Ashish Kalra For SEV, all DMA to and from guest has to use shared (un-encrypted) pages. SEV uses SWIOTLB to make this happen without requiring changes to device drivers. However, depending on workload being run, the default 64MB of SWIOTLB might not be enough and SWIOTLB may run out of

Re: [PATCH v13 01/15] iommu: Introduce attach/detach_pasid_table API

2020-11-18 Thread Jacob Pan
Hi Eric, On Wed, 18 Nov 2020 12:21:37 +0100, Eric Auger wrote: > In virtualization use case, when a guest is assigned > a PCI host device, protected by a virtual IOMMU on the guest, > the physical IOMMU must be programmed to be consistent with > the guest mappings. If the physical IOMMU

[PATCH] WIP! media: uvcvideo: Use dma_alloc_noncontiguos API

2020-11-18 Thread Ricardo Ribalda
On architectures where the is no coherent caching such as ARM use the dma_alloc_noncontiguos API and handle manually the cache flushing using dma_sync_single(). With this patch on the affected architectures we can measure up to 20x performance improvement in uvc_video_copy_data_work().

Re: [PATCH v2] iommu/vt-d: avoid unnecessory panic if iommu init fail in tboot system

2020-11-18 Thread Will Deacon
On Tue, 10 Nov 2020 15:19:08 +0800, Zhenzhong Duan wrote: > "intel_iommu=off" command line is used to disable iommu but iommu is force > enabled in a tboot system for security reason. > > However for better performance on high speed network device, a new option > "intel_iommu=tboot_noforce" is

Re: [Patch V8 0/3] iommu: Add support to change default domain of an iommu group

2020-11-18 Thread Will Deacon
On Fri, Sep 25, 2020 at 12:06:17PM -0700, Ashok Raj wrote: > Presently, the default domain of an iommu group is allocated during boot time > and it cannot be changed later. So, the device would typically be either in > identity (pass_through) mode or the device would be in DMA mode as long as the

Re: [Patch V8 1/3] iommu: Add support to change default domain of an iommu group

2020-11-18 Thread Will Deacon
On Fri, Sep 25, 2020 at 12:06:18PM -0700, Ashok Raj wrote: > From: Sai Praneeth Prakhya > > Presently, the default domain of an iommu group is allocated during boot > time and it cannot be changed later. So, the device would typically be > either in identity (also known as pass_through) mode or

Re: [Patch V8 3/3] iommu: Document usage of "/sys/kernel/iommu_groups//type" file

2020-11-18 Thread Will Deacon
On Fri, Sep 25, 2020 at 12:06:20PM -0700, Ashok Raj wrote: > From: Sai Praneeth Prakhya > > The default domain type of an iommu group can be changed by writing to > "/sys/kernel/iommu_groups//type" file. Hence, document it's usage > and more importantly spell out its limitations. > > Cc:

Re: [PATCH v2] iommu/vt-d: avoid unnecessory panic if iommu init fail in tboot system

2020-11-18 Thread Will Deacon
On Wed, Nov 18, 2020 at 07:32:25AM +0800, Lu Baolu wrote: > Please consider this patch for v5.10. Cheers, I'll stick this onto a fixes branch momentarily. Will ___ iommu mailing list iommu@lists.linux-foundation.org

[PATCH v13 15/15] iommu/smmuv3: Add PASID cache invalidation per PASID

2020-11-18 Thread Eric Auger
In order to cascade guest CFGI_CD, let's add PASID cache invalidation per PASID. Signed-off-by: Eric Auger --- v12 -> v13: - Fix !(info->flags & IOMMU_INV_PASID_FLAGS_PASID) check --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 +--- 1 file changed, 13 insertions(+), 3

[PATCH v13 14/15] iommu/smmuv3: Accept configs with more than one context descriptor

2020-11-18 Thread Eric Auger
In preparation for vSVA, let's accept userspace provided configs with more than one CD. We check the max CD against the host iommu capability and also the format (linear versus 2 level). Signed-off-by: Eric Auger Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c |

[PATCH v13 13/15] iommu/smmuv3: Report non recoverable faults

2020-11-18 Thread Eric Auger
When a stage 1 related fault event is read from the event queue, let's propagate it to potential external fault listeners, ie. users who registered a fault handler. Signed-off-by: Eric Auger --- v8 -> v9: - adapt to the removal of IOMMU_FAULT_UNRECOV_PERM_VALID: only look at

[PATCH v13 12/15] iommu/smmuv3: Implement bind/unbind_guest_msi

2020-11-18 Thread Eric Auger
The bind/unbind_guest_msi() callbacks check the domain is NESTED and redirect to the dma-iommu implementation. Signed-off-by: Eric Auger --- v6 -> v7: - remove device handle argument --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 43 + 1 file changed, 43 insertions(+)

[PATCH v13 11/15] iommu/smmuv3: Enforce incompatibility between nested mode and HW MSI regions

2020-11-18 Thread Eric Auger
Nested mode currently is not compatible with HW MSI reserved regions. Indeed MSI transactions targeting this MSI doorbells bypass the SMMU. Let's check nested mode is not attempted in such configuration. Signed-off-by: Eric Auger --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 23

[PATCH v13 10/15] iommu/smmuv3: Nested mode single MSI doorbell per domain enforcement

2020-11-18 Thread Eric Auger
In nested mode we enforce the rule that all devices belonging to the same iommu_domain share the same msi_domain. Indeed if there were several physical MSI doorbells being used within a single iommu_domain, it becomes really difficult to resolve the nested stage mapping translating into the

[PATCH v13 09/15] dma-iommu: Implement NESTED_MSI cookie

2020-11-18 Thread Eric Auger
Up to now, when the type was UNMANAGED, we used to allocate IOVA pages within a reserved IOVA MSI range. If both the host and the guest are exposed with SMMUs, each would allocate an IOVA. The guest allocates an IOVA (gIOVA) to map onto the guest MSI doorbell (gDB). The Host allocates another

[PATCH v13 08/15] iommu/smmuv3: Implement cache_invalidate

2020-11-18 Thread Eric Auger
Implement domain-selective and page-selective IOTLB invalidations. Signed-off-by: Eric Auger --- v7 -> v8: - ASID based invalidation using iommu_inv_pasid_info - check ARCHID/PASID flags in addr based invalidation - use __arm_smmu_tlb_inv_context and __arm_smmu_tlb_inv_range_nosync v6 -> v7 -

[PATCH v13 07/15] iommu/smmuv3: Allow stage 1 invalidation with unmanaged ASIDs

2020-11-18 Thread Eric Auger
With nested stage support, soon we will need to invalidate S1 contexts and ranges tagged with an unmanaged asid, this latter being managed by the guest. So let's introduce 2 helpers that allow to invalidate with externally managed ASIDs Signed-off-by: Eric Auger ---

[PATCH v13 06/15] iommu/smmuv3: Implement attach/detach_pasid_table

2020-11-18 Thread Eric Auger
On attach_pasid_table() we program STE S1 related info set by the guest into the actual physical STEs. At minimum we need to program the context descriptor GPA and compute whether the stage1 is translated/bypassed or aborted. Signed-off-by: Eric Auger --- v7 -> v8: - remove smmu->features

[PATCH v13 05/15] iommu/smmuv3: Get prepared for nested stage support

2020-11-18 Thread Eric Auger
When nested stage translation is setup, both s1_cfg and s2_cfg are set. We introduce a new smmu domain abort field that will be set upon guest stage1 configuration passing. arm_smmu_write_strtab_ent() is modified to write both stage fields in the STE and deal with the abort field. In nested

[PATCH v13 04/15] iommu/smmuv3: Allow s1 and s2 configs to coexist

2020-11-18 Thread Eric Auger
In true nested mode, both s1_cfg and s2_cfg will coexist. Let's remove the union and add a "set" field in each config structure telling whether the config is set and needs to be applied when writing the STE. In legacy nested mode, only the 2d stage is used. In true nested mode, the "set" field

[PATCH v13 03/15] iommu/arm-smmu-v3: Maintain a SID->device structure

2020-11-18 Thread Eric Auger
From: Jean-Philippe Brucker When handling faults from the event or PRI queue, we need to find the struct device associated to a SID. Add a rb_tree to keep track of SIDs. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 161

[PATCH v13 02/15] iommu: Introduce bind/unbind_guest_msi

2020-11-18 Thread Eric Auger
On ARM, MSI are translated by the SMMU. An IOVA is allocated for each MSI doorbell. If both the host and the guest are exposed with SMMUs, we end up with 2 different IOVAs allocated by each. guest allocates an IOVA (gIOVA) to map onto the guest MSI doorbell (gDB). The Host allocates another IOVA

[PATCH v13 01/15] iommu: Introduce attach/detach_pasid_table API

2020-11-18 Thread Eric Auger
In virtualization use case, when a guest is assigned a PCI host device, protected by a virtual IOMMU on the guest, the physical IOMMU must be programmed to be consistent with the guest mappings. If the physical IOMMU supports two translation stages it makes sense to program guest mappings onto the

[PATCH v13 00/15] SMMUv3 Nested Stage Setup (IOMMU part)

2020-11-18 Thread Eric Auger
This series brings the IOMMU part of HW nested paging support in the SMMUv3. The VFIO part is submitted separately. The IOMMU API is extended to support 2 new API functionalities: 1) pass the guest stage 1 configuration 2) pass stage 1 MSI bindings Then those capabilities gets implemented in the