On Wed, Jan 06, 2021 at 11:41:20AM +0800, Claire Chang wrote:
> Add the initialization function to create restricted DMA pools from
> matching reserved-memory nodes in the device tree.
>
> Signed-off-by: Claire Chang
> ---
> include/linux/device.h | 4 ++
> include/linux/swiotlb.h | 7 +-
>
If a device is not behind an IOMMU, we look up the device node and set
up the restricted DMA when the restricted-dma-pool is presented.
Signed-off-by: Claire Chang
---
drivers/of/address.c| 21 +
drivers/of/device.c | 4
drivers/of/of_private.h | 5 +
3 fil
Introduce the new compatible string, restricted-dma-pool, for restricted
DMA. One can specify the address and length of the restricted DMA memory
region by restricted-dma-pool in the device tree.
Signed-off-by: Claire Chang
---
.../reserved-memory/reserved-memory.txt | 24 +
Add the functions, swiotlb_alloc and swiotlb_free to support the
memory allocation from restricted DMA pool.
Signed-off-by: Claire Chang
---
include/linux/swiotlb.h | 6 ++
kernel/dma/direct.c | 12 +++
kernel/dma/swiotlb.c| 171 +---
3 files change
Regardless of swiotlb setting, the restricted DMA pool is preferred if
available.
The restricted DMA pools provide a basic level of protection against
the DMA overwriting buffer contents at unexpected times. However, to
protect against general data leakage and system memory corruption, the
system
Add the initialization function to create restricted DMA pools from
matching reserved-memory nodes in the device tree.
Signed-off-by: Claire Chang
---
include/linux/device.h | 4 ++
include/linux/swiotlb.h | 7 +-
kernel/dma/Kconfig | 1 +
kernel/dma/swiotlb.c| 144 ++
Added a new struct, io_tlb_mem, as the IO TLB memory pool descriptor and
moved relevant global variables into that struct.
This will be useful later to allow for restricted DMA pool.
Signed-off-by: Claire Chang
---
arch/powerpc/platforms/pseries/svm.c | 4 +-
drivers/xen/swiotlb-xen.c
This series implements mitigations for lack of DMA access control on
systems without an IOMMU, which could result in the DMA accessing the
system memory at unexpected times and/or unexpected addresses, possibly
leading to data leakage or corruption.
For example, we plan to use the PCI-e bus for Wi
Audit IOMMU Capability/Extended Capability and check if the IOMMUs have
the consistent value for features. Report out or scale to the lowest
supported when IOMMU features have incompatibility among IOMMUs.
Report out features when below features are mismatched:
- First Level 5 Level Paging Suppo
Move IOMMU capability check and sanity check code to cap_audit files.
Also implement some helper functions for sanity checks.
Signed-off-by: Kyung Min Park
---
drivers/iommu/intel/cap_audit.c | 20 +
drivers/iommu/intel/cap_audit.h | 20 +
drivers/iommu/intel/iommu.c | 76 +--
Some IOMMU Capabilities must be consistent for Shared Virtual Memory (SVM).
Audit IOMMU Capability/Extended Capabilities and check if IOMMUs have
the consistent value for features as below. When the features are not
matched among IOMMUs, disable SVMs in the platform during DMAR
initialization. Audi
Modern platforms have more than one IOMMU. Each IOMMU has its own
feature set. Some of these features must be consistent among IOMMUs.
Otherwise, these differences can lead to improper behavior in the system.
On the other hand, for some features, each IOMMU can have different
capacity values. So, d
Hi Will,
On 2021/1/6 3:04, Will Deacon wrote:
On Thu, Dec 31, 2020 at 08:53:21AM +0800, Lu Baolu wrote:
With commit c588072bba6b5 ("iommu/vt-d: Convert intel iommu driver to
the iommu ops"), the trace events for dma map/unmap have no users any
more. Remove them so that they don't show up under
Hi Will,
Happy New Year!
On 2021/1/6 3:03, Will Deacon wrote:
On Thu, Dec 31, 2020 at 08:53:20AM +0800, Lu Baolu wrote:
The VT-d hardware will ignore those Addr bits which have been masked by
the AM field in the PASID-based-IOTLB invalidation descriptor. As the
result, if the starting address
On SM8150 it's occasionally observed that the boot hangs in between the
writing of SMEs and context banks in arm_smmu_device_reset().
The problem seems to coincide with a display refresh happening after
updating the stream mapping, but before clearing - and there by
disabling translation - the con
On Tue, 22 Dec 2020 17:42:32 +0100, Stefano Garzarella wrote:
> Replace misspelled 'doamin' with 'domain' in several comments.
Applied to arm64 (for-next/iommu/fixes), thanks!
[1/1] iommu/iova: fix 'domain' typos
https://git.kernel.org/arm64/c/6775ae901ffd
Cheers,
--
Will
https://fixes.a
On Tue, 05 Jan 2021 01:36:13 +, David Woodhouse wrote:
> The AMD IOMMU initialisation registers the IRQ remapping domain for
> each IOMMU before doing the final sanity check that every I/OAPIC is
> covered.
>
> This means that the AMD irq_remapping_select() function gets invoked
> even when IR
On Tue, 05 Jan 2021 01:32:51 +, David Woodhouse wrote:
> When I made the INTCAPXT support stop gratuitously pretending to be MSI,
> I missed the fact that iommu_setup_msi() also sets the ->int_enabled
> flag. I missed this in the iommu_setup_intcapxt() code path, which means
> that a resume fro
On Tue, 5 Jan 2021 13:18:37 +0800, Dinghao Liu wrote:
> When irq_domain_get_irq_data() or irqd_cfg() fails
> at i == 0, data allocated by kzalloc() has not been
> freed before returning, which leads to memleak.
Applied to arm64 (for-next/iommu/fixes), thanks!
[1/1] iommu/intel: Fix memleak in int
Hi Konrad,
Thanks for testing it out. I have updated the patch and tested
on 5.11.0-rc2+ with dhclient successfully. Could you please help me verify
if the patch works on your side?
Thank you
NVMe driver and other applications depend on the data offset
to operate correctly. Currently when unalig
On Thu, Dec 31, 2020 at 08:53:21AM +0800, Lu Baolu wrote:
> With commit c588072bba6b5 ("iommu/vt-d: Convert intel iommu driver to
> the iommu ops"), the trace events for dma map/unmap have no users any
> more. Remove them so that they don't show up under
> /sys/kernel/debug/tracing/events/intel_iom
On Thu, Dec 31, 2020 at 08:53:20AM +0800, Lu Baolu wrote:
> The VT-d hardware will ignore those Addr bits which have been masked by
> the AM field in the PASID-based-IOTLB invalidation descriptor. As the
> result, if the starting address in the descriptor is not aligned with
> the address mask, som
On Tue, Jan 05, 2021 at 05:50:22AM +, Liu, Yi L wrote:
> > > +static void __iommu_flush_dev_iotlb(struct device_domain_info *info,
> > > + u64 addr, unsigned int mask)
> > > +{
> > > + u16 sid, qdep;
> > > +
> > > + if (!info || !info->ats_enabled)
> > > + re
Hi Liu,
url:
https://github.com/0day-ci/linux/commits/Liu-Yi-L/iommu-vt-d-Misc-fixes-on-scalable-mode/20201229-113203
base:5c8fe583cce542aa0b84adc939ce85293de36e5e
config: i386-randconfig-m021-20201229 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kin
On Tue, Jan 05, 2021 at 01:32:51AM +, David Woodhouse wrote:
> From: David Woodhouse
>
> When I made the INTCAPXT support stop gratuitously pretending to be MSI,
> I missed the fact that iommu_setup_msi() also sets the ->int_enabled
> flag. I missed this in the iommu_setup_intcapxt() code pat
On 2021/1/5 13:18, Dinghao Liu wrote:
When irq_domain_get_irq_data() or irqd_cfg() fails
at i == 0, data allocated by kzalloc() has not been
freed before returning, which leads to memleak.
Fixes: b106ee63abccb ("irq_remapping/vt-d: Enhance Intel IR driver to support
hierarchical irqdomains")
Si
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