> From: Lu Baolu
> Sent: Thursday, January 21, 2021 9:45 AM
>
> So that the uses could get chances to know what happened.
>
> Suggested-by: Ashok Raj
> Signed-off-by: Lu Baolu
> ---
> drivers/iommu/intel/svm.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git
+Isaac
On 1/22/21 3:09 AM, Chuck Lever wrote:
On Jan 18, 2021, at 1:00 PM, Robin Murphy wrote:
On 2021-01-18 16:18, Chuck Lever wrote:
On Jan 12, 2021, at 9:38 AM, Will Deacon wrote:
[Expanding cc list to include DMA-IOMMU and intel IOMMU folks]
On Fri, Jan 08, 2021 at 04:18:36PM -0500,
On 2021/1/21 20:50, Robin Murphy wrote:
> On 2021-01-21 02:04, Leizhen (ThunderTown) wrote:
>>
>>
>> On 2021/1/20 23:02, Robin Murphy wrote:
>>> On 2021-01-19 01:59, Zhen Lei wrote:
This reverts commit 52f3fab0067d6fa9e99c1b7f63265dd48ca76046.
This problem has been fixed by another
Hi Jean,
On 1/21/21 8:36 PM, Jean-Philippe Brucker wrote:
Allow drivers to query and enable IOMMU_DEV_FEAT_IOPF, which amounts to
checking whether PRI is enabled.
Signed-off-by: Jean-Philippe Brucker
Reviewed-by: Lu Baolu
Best regards,
baolu
---
Cc: David Woodhouse
Cc: Lu Baolu
---
d
On 2021-01-21 11:23, Chunyan Zhang wrote:
From: Chunyan Zhang
This patch only adds display iommu support, the driver was tested with sprd
dpu and image codec processor.
The iommu support for others would be added once finished tests with those
devices, such as a few signal processors, includin
On 2021-01-12 08:00, Robin Murphy wrote:
On 2021-01-11 14:54, Isaac J. Manjarres wrote:
The iommu_map_sg() code currently iterates through the given
scatter-gather list, and in the worst case, invokes iommu_map()
for each element in the scatter-gather list, which calls into
the IOMMU driver thro
On Thu, 21 Jan 2021 13:36:24 +0100
Jean-Philippe Brucker wrote:
> The SMMU provides a Stall model for handling page faults in platform
> devices. It is similar to PCIe PRI, but doesn't require devices to have
> their own translation cache. Instead, faulting transactions are parked
> and the OS is
> On Jan 18, 2021, at 1:00 PM, Robin Murphy wrote:
>
> On 2021-01-18 16:18, Chuck Lever wrote:
>>> On Jan 12, 2021, at 9:38 AM, Will Deacon wrote:
>>>
>>> [Expanding cc list to include DMA-IOMMU and intel IOMMU folks]
>>>
>>> On Fri, Jan 08, 2021 at 04:18:36PM -0500, Chuck Lever wrote:
On Thu, 21 Jan 2021 13:36:23 +0100
Jean-Philippe Brucker wrote:
> Copy the "Stall supported" bit, that tells whether a named component
> supports stall, into the dma-can-stall device property.
>
> Signed-off-by: Jean-Philippe Brucker
FWIW given how simple this is :
Acked-by: Jonathan Cameron
Hi Chunyan,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on v5.11-rc4 next-20210121]
[cannot apply to iommu/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
On Mon, 18 Jan 2021 21:16:08 +0800
Keqian Zhu wrote:
> On 2021/1/16 3:14, Alex Williamson wrote:
> > On Fri, 15 Jan 2021 17:26:43 +0800
> > Keqian Zhu wrote:
> >
> >> vfio_sanity_check_pfn_list() is used to check whether pfn_list of
> >> vfio_dma is empty when remove the external domain, so i
On Mon, 18 Jan 2021 20:25:09 +0800
Keqian Zhu wrote:
> On 2021/1/16 2:01, Alex Williamson wrote:
> > On Fri, 15 Jan 2021 17:26:42 +0800
> > Keqian Zhu wrote:
> >
> >> If a group with non-pinned-page dirty scope is detached with dirty
> >> logging enabled, we should fully populate the dirty bi
Hi Eric,
On 1/19/21 2:33 PM, Auger Eric wrote:
Hi Vivek,
On 1/15/21 1:13 PM, Vivek Gautam wrote:
This patch-series aims at enabling Nested stage translation in guests
using virtio-iommu as the paravirtualized iommu. The backend is supported
with Arm SMMU-v3 that provides nested stage-1 and st
On 2021-01-21 15:48, Rob Herring wrote:
On Wed, Jan 20, 2021 at 7:10 PM Robin Murphy
wrote:
On 2021-01-20 21:31, Rob Herring wrote:
On Wed, Jan 20, 2021 at 11:30 AM Robin Murphy
wrote:
On 2021-01-20 16:53, Rob Herring wrote:
On Wed, Jan 06, 2021 at 11:41:23AM +0800, Claire Chang
wrote:
I
Hi Chunyan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on v5.11-rc4 next-20210121]
[cannot apply to iommu/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest
On Wed, Jan 20, 2021 at 7:10 PM Robin Murphy wrote:
>
> On 2021-01-20 21:31, Rob Herring wrote:
> > On Wed, Jan 20, 2021 at 11:30 AM Robin Murphy wrote:
> >>
> >> On 2021-01-20 16:53, Rob Herring wrote:
> >>> On Wed, Jan 06, 2021 at 11:41:23AM +0800, Claire Chang wrote:
> Introduce the new c
Since we now keep track of page 1 via a separate pointer that already
encapsulates aliasing to page 0 as necessary, we can remove the clunky
fixup routine and simply use the relevant bases directly. The current
architecture spec (IHI0070D.a) defines SMMU_{EVENTQ,PRIQ}_{PROD,CONS} as
offsets relativ
Hi, Christoph
在 2021年01月19日 23:29, Christoph Hellwig 写道:
>> +int iommu_do_deferred_attach(struct device *dev,
>> + struct iommu_domain *domain)
>
> I'd remove the "do_" from the name, it doesn't really add any value.
>
OK.
>> +{
>> +const struct iommu_ops *ops = doma
On 2021-01-21 02:04, Leizhen (ThunderTown) wrote:
On 2021/1/20 23:02, Robin Murphy wrote:
On 2021-01-19 01:59, Zhen Lei wrote:
This reverts commit 52f3fab0067d6fa9e99c1b7f63265dd48ca76046.
This problem has been fixed by another patch. The original method had side
effects, it was not mapped t
On ARM systems, some platform devices behind an IOMMU may support stall,
which is the ability to recover from page faults. Let the firmware tell us
when a device supports stall.
Reviewed-by: Rob Herring
Signed-off-by: Jean-Philippe Brucker
---
.../devicetree/bindings/iommu/iommu.txt| 18
Copy the "Stall supported" bit, that tells whether a named component
supports stall, into the dma-can-stall device property.
Signed-off-by: Jean-Philippe Brucker
---
drivers/acpi/arm64/iort.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/acpi/arm64/iort.c b/drive
Allow drivers to query and enable IOMMU_DEV_FEAT_IOPF, which amounts to
checking whether PRI is enabled.
Signed-off-by: Jean-Philippe Brucker
---
Cc: David Woodhouse
Cc: Lu Baolu
---
drivers/iommu/intel/iommu.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/dri
When handling faults from the event or PRI queue, we need to find the
struct device associated with a SID. Add a rb_tree to keep track of
SIDs.
Acked-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 13 +-
drivers/iommu/arm/arm-smmu-v3
The SMMU provides a Stall model for handling page faults in platform
devices. It is similar to PCIe PRI, but doesn't require devices to have
their own translation cache. Instead, faulting transactions are parked
and the OS is given a chance to fix the page tables and retry the
transaction.
Enable
Some systems allow devices to handle I/O Page Faults in the core mm. For
example systems implementing the PCIe PRI extension or Arm SMMU stall
model. Infrastructure for reporting these recoverable page faults was
added to the IOMMU core by commit 0c830e6b3282 ("iommu: Introduce device
fault report
The IOPF (I/O Page Fault) feature is now enabled independently from the
SVA feature, because some IOPF implementations are device-specific and
do not require IOMMU support for PCIe PRI or Arm SMMU stall.
Enable IOPF unconditionally when enabling SVA for now. In the future, if
a device driver imple
Add stall support to the SMMUv3, along with a common I/O Page Fault
handler.
Changes since v9 [1]:
* Style changes suggested by Jonathan
* Fixes to patch 10 pointed out by Robin
* In patch 10, don't register the mm fault handler when enabling
IOMMU_DEV_FEAT_IOPF, because that feature only indica
Some devices manage I/O Page Faults (IOPF) themselves instead of relying
on PCIe PRI or Arm SMMU stall. Allow their drivers to enable SVA without
mandating IOMMU-managed IOPF. The other device drivers now need to first
enable IOMMU_DEV_FEAT_IOPF before enabling IOMMU_DEV_FEAT_SVA. Enabling
IOMMU_DE
The pasid-num-bits property shouldn't need a dedicated fwspec field,
it's a job for device properties. Add properties for IORT, and access
the number of PASID bits using device_property_read_u32().
Suggested-by: Robin Murphy
Acked-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
---
i
Commit 986d5ecc5699 ("iommu: Move fwspec->iommu_priv to struct
dev_iommu") removed iommu_priv from fwspec and commit 5702ee24182f
("ACPI/IORT: Check ATS capability in root complex nodes") added @flags.
Update the struct doc.
Acked-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
---
in
Hi, Christoph
Thanks for the comment.
在 2021年01月19日 23:26, Christoph Hellwig 写道:
> On Tue, Jan 19, 2021 at 07:16:15PM +0800, Lianbo Jiang wrote:
>> +static DEFINE_STATIC_KEY_FALSE(__deferred_attach);
> Why the strange underscores? Wouldn't iommu_deferred_attach_enabled
The variable is defined wi
From: Chunyan Zhang
This patch only adds display iommu support, the driver was tested with sprd
dpu and image codec processor.
The iommu support for others would be added once finished tests with those
devices, such as a few signal processors, including VSP(video),
GSP(graphic), ISP(image), and
From: Chunyan Zhang
This patch adds bindings to support display and Image codec(jpeg) iommu
instance.
The iommu support for others would be added once finished tests with those
devices, such as a few signal processors, including VSP(video),
GSP(graphic), ISP(image), and camera CPP, etc.
Signed-
From: Chunyan Zhang
Changes since RFC v2:
* Addressed Robin's comments:
- Add COMPILE_TEST support;
- Use DMA allocator for PTE;
- Revised to avoid resource leak issue;
- Added ->iotlb_sync implemented;
- Moved iommu group allocation to probe;
- Changed some function names to make them sprd speci
On Wed, Jan 20, 2021 at 7:01 AM Wei Liu wrote:
>
> The IOMMU code needs more work. We're sure for now the IRQ remapping
> hooks are not applicable when Linux is the root partition.
>
> Signed-off-by: Wei Liu
> Acked-by: Joerg Roedel
> Reviewed-by: Vitaly Kuznetsov
> ---
> drivers/iommu/hyperv-
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